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| author | jacquesguan <jacquesguan@me.com> | 2021-12-20 14:25:06 +0800 |
|---|---|---|
| committer | jacquesguan <jacquesguan@me.com> | 2021-12-20 14:25:06 +0800 |
| commit | 9c11e952868342dfbf0efedd246dac6191ee98d7 (patch) | |
| tree | 533524134be091d5205497030449c91e2a7a8a77 | |
| parent | 0060060fef5da582799a706b6ba8c6ec9fcda2a2 (diff) | |
| download | llvm-9c11e952868342dfbf0efedd246dac6191ee98d7.zip llvm-9c11e952868342dfbf0efedd246dac6191ee98d7.tar.gz llvm-9c11e952868342dfbf0efedd246dac6191ee98d7.tar.bz2 | |
[Clang][RISCV] Fix upper bound of RISC-V V type in debug info
The UpperBound of RVV type in debug info should be elements count minus one,
as the LowerBound start from zero.
Reviewed By: HsiangKai
Differential Revision: https://reviews.llvm.org/D115430
| -rw-r--r-- | clang/lib/CodeGen/CGDebugInfo.cpp | 4 | ||||
| -rw-r--r-- | clang/test/CodeGen/RISCV/riscv-v-debuginfo.c | 6 |
2 files changed, 6 insertions, 4 deletions
diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp b/clang/lib/CodeGen/CGDebugInfo.cpp index 0de089b..89ec9f1 100644 --- a/clang/lib/CodeGen/CGDebugInfo.cpp +++ b/clang/lib/CodeGen/CGDebugInfo.cpp @@ -768,7 +768,7 @@ llvm::DIType *CGDebugInfo::CreateType(const BuiltinType *BT) { } // Element count = (VLENB / SEW) x LMUL - SmallVector<int64_t, 9> Expr( + SmallVector<int64_t, 12> Expr( // The DW_OP_bregx operation has two operands: a register which is // specified by an unsigned LEB128 number, followed by a signed LEB128 // offset. @@ -782,6 +782,8 @@ llvm::DIType *CGDebugInfo::CreateType(const BuiltinType *BT) { Expr.push_back(llvm::dwarf::DW_OP_div); else Expr.push_back(llvm::dwarf::DW_OP_mul); + // Element max index = count - 1 + Expr.append({llvm::dwarf::DW_OP_constu, 1, llvm::dwarf::DW_OP_minus}); auto *LowerBound = llvm::ConstantAsMetadata::get(llvm::ConstantInt::getSigned( diff --git a/clang/test/CodeGen/RISCV/riscv-v-debuginfo.c b/clang/test/CodeGen/RISCV/riscv-v-debuginfo.c index b5ed0c5..f0e405a 100644 --- a/clang/test/CodeGen/RISCV/riscv-v-debuginfo.c +++ b/clang/test/CodeGen/RISCV/riscv-v-debuginfo.c @@ -9,7 +9,7 @@ __rvv_int16m2_t f1(__rvv_int16m2_t arg_0, __rvv_int16m2_t arg_1, int64_t arg_2) } // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con -// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul)) +// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul, DW_OP_constu, 1, DW_OP_minus)) __rvv_int16mf2_t f2(__rvv_int16mf2_t arg_0, __rvv_int16mf2_t arg_1, int64_t arg_2) { __rvv_int16mf2_t ret; @@ -17,7 +17,7 @@ __rvv_int16mf2_t f2(__rvv_int16mf2_t arg_0, __rvv_int16mf2_t arg_1, int64_t arg_ } // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con -// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div)) +// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 1, DW_OP_minus)) __rvv_int32mf2_t f3(__rvv_int32mf2_t arg_0, __rvv_int32mf2_t arg_1, int64_t arg_2) { __rvv_int32mf2_t ret; @@ -25,4 +25,4 @@ __rvv_int32mf2_t f3(__rvv_int32mf2_t arg_0, __rvv_int32mf2_t arg_1, int64_t arg_ } // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con -// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div)) +// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 1, DW_OP_minus)) |