Add Hexagon Support

Differential Revision: https://reviews.llvm.org/D47791

llvm-svn: 334637

7 files changed, 104 insertions, 0 deletions

diff --git a/lld/ELF/Arch/Hexagon.cpp b/lld/ELF/Arch/Hexagon.cpp
new file mode 100644
index 0000000..ed000cc
--- /dev/null
+++ b/lld/ELF/Arch/Hexagon.cpp
@@ -0,0 +1,84 @@
+//===-- Hexagon.cpp -------------------------------------------------------===//
+//
+//                             The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "InputFiles.h"
+#include "Symbols.h"
+#include "Target.h"
+#include "lld/Common/ErrorHandler.h"
+#include "llvm/BinaryFormat/ELF.h"
+#include "llvm/Object/ELF.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+using namespace llvm::object;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+namespace {
+class Hexagon final : public TargetInfo {
+public:
+  uint32_t calcEFlags() const override;
+  uint32_t applyMask(uint32_t Mask, uint32_t Data) const;
+  RelExpr getRelExpr(RelType Type, const Symbol &S,
+                     const uint8_t *Loc) const override;
+  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+};
+} // namespace
+
+// Support V60 only at the moment.
+uint32_t Hexagon::calcEFlags() const {
+  return 0x60;
+}
+
+uint32_t Hexagon::applyMask(uint32_t Mask, uint32_t Data) const {
+  uint32_t Result = 0;
+  size_t Off = 0;
+
+  for (size_t Bit = 0; Bit != 32; ++Bit) {
+    uint32_t ValBit = (Data >> Off) & 1;
+    uint32_t MaskBit = (Mask >> Bit) & 1;
+    if (MaskBit) {
+      Result |= (ValBit << Bit);
+      ++Off;
+    }
+  }
+  return Result;
+}
+
+RelExpr Hexagon::getRelExpr(RelType Type, const Symbol &S,
+                                 const uint8_t *Loc) const {
+  switch (Type) {
+  case R_HEX_B22_PCREL:
+    return R_PC;
+  default:
+    return R_ABS;
+  }
+}
+
+static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
+
+void Hexagon::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
+  switch (Type) {
+  case R_HEX_NONE:
+    break;
+  case R_HEX_B22_PCREL:
+    or32le(Loc, applyMask(0x01ff3ffe, ((Val >> 2) & 0x3fffff)));
+    break;
+  default:
+    error(getErrorLocation(Loc) + "unrecognized reloc " + toString(Type));
+    break;
+  }
+}
+
+TargetInfo *elf::getHexagonTargetInfo() {
+  static Hexagon Target;
+  return &Target;
+}
diff --git a/lld/ELF/CMakeLists.txt b/lld/ELF/CMakeLists.txt
index af2bed3..fb2f53a 100644
--- a/lld/ELF/CMakeLists.txt
+++ b/lld/ELF/CMakeLists.txt
@@ -12,6 +12,7 @@ add_lld_library(lldELF
   Arch/AMDGPU.cpp
   Arch/ARM.cpp
   Arch/AVR.cpp
+  Arch/Hexagon.cpp
   Arch/Mips.cpp
   Arch/MipsArchTree.cpp
   Arch/PPC.cpp
diff --git a/lld/ELF/Target.cpp b/lld/ELF/Target.cpp
index c19cb5f..ad5821c 100644
--- a/lld/ELF/Target.cpp
+++ b/lld/ELF/Target.cpp
@@ -60,6 +60,8 @@ TargetInfo *elf::getTarget() {
     return getARMTargetInfo();
   case EM_AVR:
     return getAVRTargetInfo();
+  case EM_HEXAGON:
+    return getHexagonTargetInfo();
   case EM_MIPS:
     switch (Config->EKind) {
     case ELF32LEKind:
diff --git a/lld/ELF/Target.h b/lld/ELF/Target.h
index b04e6c4..ee1a7a4 100644
--- a/lld/ELF/Target.h
+++ b/lld/ELF/Target.h
@@ -140,6 +140,7 @@ TargetInfo *getAArch64TargetInfo();
 TargetInfo *getAMDGPUTargetInfo();
 TargetInfo *getARMTargetInfo();
 TargetInfo *getAVRTargetInfo();
+TargetInfo *getHexagonTargetInfo();
 TargetInfo *getPPC64TargetInfo();
 TargetInfo *getPPCTargetInfo();
 TargetInfo *getSPARCV9TargetInfo();
diff --git a/lld/test/ELF/Inputs/hexagon.s b/lld/test/ELF/Inputs/hexagon.s
new file mode 100644
index 0000000..921a0c4
--- /dev/null
+++ b/lld/test/ELF/Inputs/hexagon.s
@@ -0,0 +1,6 @@
+.global _start
+_start:
+  nop
+.global foo
+foo:
+  jumpr lr
diff --git a/lld/test/ELF/hexagon.s b/lld/test/ELF/hexagon.s
new file mode 100644
index 0000000..596b3d0
--- /dev/null
+++ b/lld/test/ELF/hexagon.s
@@ -0,0 +1,9 @@
+# REQUIRES: hexagon
+# RUN: llvm-mc -filetype=obj -triple=hexagon-unknown-elf %s -o %t
+# RUN: llvm-mc -filetype=obj -triple=hexagon-unknown-elf %S/Inputs/hexagon.s -o %t2
+# RUN: ld.lld %t2 %t  -o %t3
+# RUN: llvm-objdump -d  %t3 | FileCheck %s
+
+# R_HEX_B22_PCREL
+call #_start
+# CHECK: call 0x11000
diff --git a/lld/test/lit.cfg.py b/lld/test/lit.cfg.py
index 41b57e5..2688038 100644
--- a/lld/test/lit.cfg.py
+++ b/lld/test/lit.cfg.py
@@ -65,6 +65,7 @@ llvm_config.feature_config(
                           'AMDGPU': 'amdgpu',
                           'ARM': 'arm',
                           'AVR': 'avr',
+                          'Hexagon': 'hexagon',
                           'Mips': 'mips',
                           'PowerPC': 'ppc',
                           'Sparc': 'sparc',