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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-16 00:53:31 -0400 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-01-07 10:15:29 -0500 |
| commit | 9150d6bd738a3d68ee1597751a874913e04b49d8 (patch) | |
| tree | ba524ee44226829fcccdbb4d589faf26a2db47cf | |
| parent | e130eef58814d12b0490033fbedcf75db8a4f148 (diff) | |
| download | llvm-9150d6bd738a3d68ee1597751a874913e04b49d8.zip llvm-9150d6bd738a3d68ee1597751a874913e04b49d8.tar.gz llvm-9150d6bd738a3d68ee1597751a874913e04b49d8.tar.bz2 | |
AMDGPU/GlobalISel: Select llvm.amdgcn.wqm.vote
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SOPInstructions.td | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.vote.ll | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll | 21 |
3 files changed, 20 insertions, 8 deletions
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index c7893d3..a89416d 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -170,14 +170,14 @@ let Defs = [SCC] in { let WaveSizePredicate = isWave32 in { def : GCNPat < (int_amdgcn_wqm_vote i1:$src0), - (S_WQM_B32 $src0) + (S_WQM_B32 SSrc_b32:$src0) >; } let WaveSizePredicate = isWave64 in { def : GCNPat < (int_amdgcn_wqm_vote i1:$src0), - (S_WQM_B64 $src0) + (S_WQM_B64 SSrc_b64:$src0) >; } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.vote.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.vote.ll new file mode 100644 index 0000000..a0913ee --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.vote.ll @@ -0,0 +1,3 @@ +; Runs original SDAG test with -global-isel +; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %S/../llvm.amdgcn.wqm.vote.ll | FileCheck -enable-var-scope -check-prefixes=CHECK,WAVE64 %S/../llvm.amdgcn.wqm.vote.ll +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %S/../llvm.amdgcn.wqm.vote.ll | FileCheck -enable-var-scope -check-prefixes=CHECK,WAVE32 %S/../llvm.amdgcn.wqm.vote.ll diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll index 57af85b..07aefa2 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll @@ -1,8 +1,10 @@ -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CHECK %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CHECK,WAVE64 %s +; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CHECK,WAVE32 %s ;CHECK-LABEL: {{^}}ret: ;CHECK: v_cmp_eq_u32_e32 [[CMP:[^,]+]], v0, v1 -;CHECK: s_wqm_b64 [[WQM:[^,]+]], [[CMP]] +;WAVE64: s_wqm_b64 [[WQM:[^,]+]], [[CMP]] +;WAVE32: s_wqm_b32 [[WQM:[^,]+]], [[CMP]] ;CHECK: v_cndmask_b32_e64 v0, 0, 1.0, [[WQM]] define amdgpu_ps float @ret(i32 %v0, i32 %v1) #1 { main_body: @@ -13,7 +15,8 @@ main_body: } ;CHECK-LABEL: {{^}}true: -;CHECK: s_wqm_b64 +;WAVE64: s_wqm_b64 +;WAVE32: s_wqm_b32 define amdgpu_ps float @true() #1 { main_body: %w = call i1 @llvm.amdgcn.wqm.vote(i1 true) @@ -22,7 +25,8 @@ main_body: } ;CHECK-LABEL: {{^}}false: -;CHECK: s_wqm_b64 +;WAVE64: s_wqm_b64 +;WAVE32: s_wqm_b32 define amdgpu_ps float @false() #1 { main_body: %w = call i1 @llvm.amdgcn.wqm.vote(i1 false) @@ -32,8 +36,13 @@ main_body: ;CHECK-LABEL: {{^}}kill: ;CHECK: v_cmp_eq_u32_e32 [[CMP:[^,]+]], v0, v1 -;CHECK: s_wqm_b64 [[WQM:[^,]+]], [[CMP]] -;CHECK: s_and_b64 exec, exec, [[WQM]] + +;WAVE64: s_wqm_b64 [[WQM:[^,]+]], [[CMP]] +;WAVE64: s_and_b64 exec, exec, [[WQM]] + +;WAVE32: s_wqm_b32 [[WQM:[^,]+]], [[CMP]] +;WAVE32: s_and_b32 exec_lo, exec_lo, [[WQM]] + ;CHECK: s_endpgm define amdgpu_ps void @kill(i32 %v0, i32 %v1) #1 { main_body: |