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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-01-22 18:42:49 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-01-22 18:42:49 +0000 |
| commit | 8d903029e86eb771fb6b6b2d6f1ad7290f23d389 (patch) | |
| tree | e66eca4e23af034504911bc9ebd6b6e2a71b045a | |
| parent | ee0930821a95ba5f8f5e98a85f3bd5316f9173d4 (diff) | |
| download | llvm-8d903029e86eb771fb6b6b2d6f1ad7290f23d389.zip llvm-8d903029e86eb771fb6b6b2d6f1ad7290f23d389.tar.gz llvm-8d903029e86eb771fb6b6b2d6f1ad7290f23d389.tar.bz2 | |
AMDGPU: Don't use separate mulhu/mulhs Pats
llvm-svn: 258515
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 89692ab..b941c76 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -1754,14 +1754,14 @@ defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169, 0x285>, "v_mul_lo_u32", VOP_I32_I32_I32 >; defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a, 0x286>, "v_mul_hi_u32", - VOP_I32_I32_I32 + VOP_I32_I32_I32, mulhu >; defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b, 0x285>, "v_mul_lo_i32", VOP_I32_I32_I32 >; defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32", - VOP_I32_I32_I32 + VOP_I32_I32_I32, mulhs >; } // isCommutable = 1, SchedRW = [WriteQuarterRate32] @@ -2772,16 +2772,6 @@ def : Pat < def : IMad24Pat<V_MAD_I32_I24>; def : UMad24Pat<V_MAD_U32_U24>; -def : Pat < - (mulhu i32:$src0, i32:$src1), - (V_MUL_HI_U32 $src0, $src1) ->; - -def : Pat < - (mulhs i32:$src0, i32:$src1), - (V_MUL_HI_I32 $src0, $src1) ->; - defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>; def : ROTRPattern <V_ALIGNBIT_B32>; |