diff options
| author | Alex Bradbury <asb@igalia.com> | 2023-08-02 10:40:04 +0100 |
|---|---|---|
| committer | Alex Bradbury <asb@igalia.com> | 2023-08-02 10:40:38 +0100 |
| commit | 8acb8a143f5075cf8f9ff0818e89b1f80827f0e9 (patch) | |
| tree | eee24cc59dd349884aef3d5ba5f67e7e34d3b9de | |
| parent | 24f320e48c83a70afd19165fe0bf5a5a01b88a64 (diff) | |
| download | llvm-8acb8a143f5075cf8f9ff0818e89b1f80827f0e9.zip llvm-8acb8a143f5075cf8f9ff0818e89b1f80827f0e9.tar.gz llvm-8acb8a143f5075cf8f9ff0818e89b1f80827f0e9.tar.bz2 | |
[RISCV] Make Zcf and Zcd imply the F and D extensions respectively
This was an omission in the spec that has now been addressed
https://github.com/riscv/riscv-code-size-reduction/pull/224.
Differential Revision: https://reviews.llvm.org/D156314
| -rw-r--r-- | llvm/lib/Support/RISCVISAInfo.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/attributes.ll | 6 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/attribute-arch.s | 4 |
3 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index e6d6797..093eaf5 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -956,9 +956,9 @@ static const char *ImpliedExtsXTHeadVdot[] = {"v"}; static const char *ImpliedExtsXsfvcp[] = {"zve32x"}; static const char *ImpliedExtsZacas[] = {"a"}; static const char *ImpliedExtsZcb[] = {"zca"}; -static const char *ImpliedExtsZcd[] = {"zca"}; +static const char *ImpliedExtsZcd[] = {"d", "zca"}; static const char *ImpliedExtsZce[] = {"zcb", "zcmp", "zcmt"}; -static const char *ImpliedExtsZcf[] = {"zca"}; +static const char *ImpliedExtsZcf[] = {"f", "zca"}; static const char *ImpliedExtsZcmp[] = {"zca"}; static const char *ImpliedExtsZcmt[] = {"zca"}; static const char *ImpliedExtsZdinx[] = {"zfinx"}; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 2fe6cd0..dc087fe 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -231,8 +231,8 @@ ; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0" ; RV32ZCA: .attribute 5, "rv32i2p1_zca1p0" ; RV32ZCB: .attribute 5, "rv32i2p1_zca1p0_zcb1p0" -; RV32ZCD: .attribute 5, "rv32i2p1_zca1p0_zcd1p0" -; RV32ZCF: .attribute 5, "rv32i2p1_zca1p0_zcf1p0" +; RV32ZCD: .attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0" +; RV32ZCF: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0" ; RV32ZCMP: .attribute 5, "rv32i2p1_zca1p0_zcmp1p0" ; RV32ZCMT: .attribute 5, "rv32i2p1_zicsr2p0_zca1p0_zcmt1p0" ; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0" @@ -319,7 +319,7 @@ ; RV64ZTSO: .attribute 5, "rv64i2p1_ztso0p1" ; RV64ZCA: .attribute 5, "rv64i2p1_zca1p0" ; RV64ZCB: .attribute 5, "rv64i2p1_zca1p0_zcb1p0" -; RV64ZCD: .attribute 5, "rv64i2p1_zca1p0_zcd1p0" +; RV64ZCD: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0" ; RV64ZCMP: .attribute 5, "rv64i2p1_zca1p0_zcmp1p0" ; RV64ZCMT: .attribute 5, "rv64i2p1_zicsr2p0_zca1p0_zcmt1p0" ; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 9dcaf03..8f27831 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -229,10 +229,10 @@ # CHECK: attribute 5, "rv32i2p1_zca1p0" .attribute arch, "rv32izcd1p0" -# CHECK: attribute 5, "rv32i2p1_zca1p0_zcd1p0" +# CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0" .attribute arch, "rv32izcf1p0" -# CHECK: attribute 5, "rv32i2p1_zca1p0_zcf1p0" +# CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0" .attribute arch, "rv32izcb1p0" # CHECK: attribute 5, "rv32i2p1_zca1p0_zcb1p0" |