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| author | Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com> | 2015-11-16 17:05:01 +0000 |
|---|---|---|
| committer | Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com> | 2015-11-16 17:05:01 +0000 |
| commit | 88faf6d6979dff876aabbec690b7096d123f3092 (patch) | |
| tree | e7de1ce1e4bbef175feedfc1884ab0dbb87d2526 | |
| parent | ed5cc95d2297f9a7c12ea6a4fd3c517c5bc9dfac (diff) | |
| download | llvm-88faf6d6979dff876aabbec690b7096d123f3092.zip llvm-88faf6d6979dff876aabbec690b7096d123f3092.tar.gz llvm-88faf6d6979dff876aabbec690b7096d123f3092.tar.bz2 | |
[mips] Disable code generation through FastISel for MIPS32R6.
Reviewers: dsanders
Subscribers: llvm-commits, dsanders
Differential Revision: http://reviews.llvm.org/D14708
llvm-svn: 253225
| -rw-r--r-- | llvm/lib/Target/Mips/MipsFastISel.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll | 27 |
2 files changed, 30 insertions, 3 deletions
diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp index 23b0215..e9eaf81 100644 --- a/llvm/lib/Target/Mips/MipsFastISel.cpp +++ b/llvm/lib/Target/Mips/MipsFastISel.cpp @@ -192,10 +192,10 @@ public: TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) { MFI = funcInfo.MF->getInfo<MipsFunctionInfo>(); Context = &funcInfo.Fn->getContext(); + bool ISASupported = !Subtarget->hasMips32r6() && Subtarget->hasMips32(); TargetSupported = - ((TM.getRelocationModel() == Reloc::PIC_) && - ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) && - (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32()))); + ISASupported && (TM.getRelocationModel() == Reloc::PIC_) && + (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32()); UnsupportedFPMode = Subtarget->isFP64bit(); } diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll b/llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll new file mode 100644 index 0000000..203e5a7 --- /dev/null +++ b/llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll @@ -0,0 +1,27 @@ +; RUN: llc -march=mips -mcpu=mips2 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: llc -march=mips -mcpu=mips3 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: llc -march=mips -mcpu=mips4 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s + +; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s + +; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: llc -march=mips -mcpu=mips64r2 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: llc -march=mips -mcpu=mips64r3 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: llc -march=mips -mcpu=mips64r5 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s + +; CHECK: FastISel missed terminator: ret i32 0 + +define i32 @foo() { +entry: + ret i32 0 +} |