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authorShuxin Yang <shuxin.llvm@gmail.com>2012-12-04 03:28:32 +0000
committerShuxin Yang <shuxin.llvm@gmail.com>2012-12-04 03:28:32 +0000
commit86c0e232b7ce1fe640d474c7dcb57f1e19253c7c (patch)
tree90cf3a47027a0c374ab6df7f818784db809a6684
parentbeb15ca8f09ab596f3d16b622226ed563064645a (diff)
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rdar://12329730 (2nd part, revised)
The type of shirt-right (logical or arithemetic) should remain unchanged when transforming "X << C1 >> C2" into "X << (C1-C2)" llvm-svn: 169209
-rw-r--r--llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp3
-rw-r--r--llvm/test/Transforms/InstCombine/shift.ll2
2 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index c65076e..c832ca5 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -876,7 +876,8 @@ Value *InstCombiner::SimplifyShrShlDemandedBits(Instruction *Shr,
New->setHasNoUnsignedWrap(Orig->hasNoUnsignedWrap());
} else {
Constant *Amt = ConstantInt::get(VarX->getType(), ShrAmt - ShlAmt);
- New = BinaryOperator::CreateLShr(VarX, Amt);
+ New = isLshr ? BinaryOperator::CreateLShr(VarX, Amt) :
+ BinaryOperator::CreateAShr(VarX, Amt);
}
return InsertNewInstWith(New, *Shl);
diff --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll
index b152816..fad0bd7 100644
--- a/llvm/test/Transforms/InstCombine/shift.ll
+++ b/llvm/test/Transforms/InstCombine/shift.ll
@@ -723,7 +723,7 @@ define i32 @test60(i32 %x) {
%or = or i32 %shl, 1
ret i32 %or
; CHECK: @test60
-; CHECK: lshr i32 %x, 3
+; CHECK: ashr i32 %x, 3
}