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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-06-20 18:28:02 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-06-20 18:28:02 +0000 |
commit | 7f67b3590168b88d69bc1ab067ad3075c7c28e62 (patch) | |
tree | ed381c9f4e5b4984839168cae91ac0f66cabba13 | |
parent | e7a35539c5521985d75e89f3329a84fed09584e4 (diff) | |
download | llvm-7f67b3590168b88d69bc1ab067ad3075c7c28e62.zip llvm-7f67b3590168b88d69bc1ab067ad3075c7c28e62.tar.gz llvm-7f67b3590168b88d69bc1ab067ad3075c7c28e62.tar.bz2 |
AMDGPU: Fix crash with undef vreg input operand
llvm-svn: 305814
-rw-r--r-- | llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 2 | ||||
-rw-r--r-- | llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir | 21 |
2 files changed, 22 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp index e10f1ed..bf6b7c5 100644 --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -470,7 +470,7 @@ static MachineOperand *getImmOrMaterializedImm(MachineRegisterInfo &MRI, return &Op; MachineInstr *Def = MRI.getVRegDef(Op.getReg()); - if (Def->isMoveImmediate()) { + if (Def && Def->isMoveImmediate()) { MachineOperand &ImmSrc = Def->getOperand(1); if (ImmSrc.isImm()) return &ImmSrc; diff --git a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir index 62b47be..4d8e608 100644 --- a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir +++ b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir @@ -68,6 +68,10 @@ ret void } + define amdgpu_kernel void @undefined_vreg_operand() { + unreachable + } + declare i32 @llvm.amdgcn.workitem.id.x() #1 attributes #0 = { nounwind } @@ -856,3 +860,20 @@ body: | S_ENDPGM ... +--- +# There is only an undef use operand for %1, so there is no +# corresponding defining instruction + +name: undefined_vreg_operand +tracksRegLiveness: true +registers: + - { id: 0, class: vgpr_32, preferred-register: '' } + - { id: 1, class: vgpr_32, preferred-register: '' } + - { id: 2, class: vgpr_32, preferred-register: '' } +body: | + bb.0: + %0 = V_MOV_B32_e32 0, implicit %exec + %2 = V_XOR_B32_e64 killed %0, undef %1, implicit %exec + S_ENDPGM + +... |