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| author | Ruiling Song <ruiling.song@amd.com> | 2022-04-12 20:50:44 +0800 |
|---|---|---|
| committer | Ruiling Song <ruiling.song@amd.com> | 2022-04-14 13:30:48 +0800 |
| commit | 7c87d75d74f3c2943b286b239ec6ff96fc5109c7 (patch) | |
| tree | 6e693cfc90ae9f6fcecc80e8516ad8d3f1b26f17 | |
| parent | bfafa105aab05e2c243e74114739b7d37f8ab0be (diff) | |
| download | llvm-7c87d75d74f3c2943b286b239ec6ff96fc5109c7.zip llvm-7c87d75d74f3c2943b286b239ec6ff96fc5109c7.tar.gz llvm-7c87d75d74f3c2943b286b239ec6ff96fc5109c7.tar.bz2 | |
test: Don't depend on behavior of switch lower in one test. NFC
This is a preliminary change to update the test so that it does not
depend on how switch-case will be lowered. The following change will
lower switch-case more optimally that will make the test no longer
valid.
Reviewed by: arsenm
Differential Revision: https://reviews.llvm.org/D123606
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll | 26 |
1 files changed, 20 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll b/llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll index f34e413..ec9cf02 100644 --- a/llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll +++ b/llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll @@ -47,11 +47,20 @@ cond.true: ; preds = %entry br i1 %phi.cmp, label %common.ret, label %cond.true20 cond.true20: ; preds = %cond.true - %trunc1 = trunc i32 %0 to i8 - switch i8 %trunc, label %common.ret [ - i8 44, label %sw.bb - i8 0, label %if.end.i.i2285 - ] + %v = zext i8 %trunc to i32 + br label %NodeBlock + +NodeBlock: ; preds = %cond.true20 + %Pivot = icmp slt i32 %v, 44 + br i1 %Pivot, label %LeafBlock, label %LeafBlock1 + +LeafBlock1: ; preds = %NodeBlock + %SwitchLeaf2 = icmp eq i32 %v, 44 + br i1 %SwitchLeaf2, label %sw.bb, label %NewDefault + +LeafBlock: ; preds = %NodeBlock + %SwitchLeaf = icmp eq i32 %v, 0 + br i1 %SwitchLeaf, label %if.end.i.i2285, label %NewDefault sw.bb: ; preds = %cond.true20 %10 = load float, float* null, align 4 @@ -76,7 +85,12 @@ common.ret.critedge: ; preds = %entry store i32 0, i32* null, align 4 br label %common.ret -common.ret: ; preds = %if.end.i.i2285, %if.end627.sink.split, %cond.end579, %bsdf_alloc.exit2188, %if.end511, %common.ret.critedge, %if.then443, %sw.bb, %cond.true20, %cond.true +NewDefault: ; preds = %LeafBlock1, %LeafBlock + %phi.store = phi i32 [0, %LeafBlock], [1, %LeafBlock1] + store i32 %phi.store, i32* null, align 4 + br label %common.ret + +common.ret: ; preds = %if.end.i.i2285, %if.end627.sink.split, %cond.end579, %bsdf_alloc.exit2188, %if.end511, %common.ret.critedge, %if.then443, %sw.bb, %NewDefault, %cond.true ret void if.end511: ; preds = %if.then443 |