[RISCV] Update some tests to use a common check prefix. NFC.

To make it easier to see that the codegen is the same across different options.

3 files changed, 108 insertions, 254 deletions

diff --git a/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
index d561145..1360a29 100644
--- a/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
@@ -1,10 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=RV32I
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadbb -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=RV32XTHEADBB,RV32XTHEADBB-NOB
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32XTHEADBB,RV32XTHEADBB-NOB
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadbb,+b -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=RV32XTHEADBB,RV32XTHEADBB-B
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32XTHEADBB,RV32XTHEADBB-B
 
 declare i32 @llvm.ctlz.i32(i32, i1)
 
@@ -354,19 +354,12 @@ define i32 @sexti1_i32_2(i1 %a) nounwind {
 
 ; Make sure we don't use not+th.ext
 define zeroext i8 @sexti1_i32_setcc(i32 signext %a) {
-; RV32I-LABEL: sexti1_i32_setcc:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a0, a0, 31
-; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    zext.b a0, a0
-; RV32I-NEXT:    ret
-;
-; RV32XTHEADBB-LABEL: sexti1_i32_setcc:
-; RV32XTHEADBB:       # %bb.0:
-; RV32XTHEADBB-NEXT:    srli a0, a0, 31
-; RV32XTHEADBB-NEXT:    addi a0, a0, -1
-; RV32XTHEADBB-NEXT:    zext.b a0, a0
-; RV32XTHEADBB-NEXT:    ret
+; CHECK-LABEL: sexti1_i32_setcc:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srli a0, a0, 31
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    zext.b a0, a0
+; CHECK-NEXT:    ret
   %icmp = icmp sgt i32 %a, -1
   %sext = sext i1 %icmp to i8
   ret i8 %sext
@@ -374,19 +367,12 @@ define zeroext i8 @sexti1_i32_setcc(i32 signext %a) {
 
 ; Make sure we don't use seqz+th.ext instead of snez+addi
 define i32 @sexti1_i32_setcc_2(i32 %a, i32 %b) {
-; RV32I-LABEL: sexti1_i32_setcc_2:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    snez a0, a0
-; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    ret
-;
-; RV32XTHEADBB-LABEL: sexti1_i32_setcc_2:
-; RV32XTHEADBB:       # %bb.0:
-; RV32XTHEADBB-NEXT:    xor a0, a0, a1
-; RV32XTHEADBB-NEXT:    snez a0, a0
-; RV32XTHEADBB-NEXT:    addi a0, a0, -1
-; RV32XTHEADBB-NEXT:    ret
+; CHECK-LABEL: sexti1_i32_setcc_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xor a0, a0, a1
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    ret
   %icmp = icmp eq i32 %a, %b
   %sext = sext i1 %icmp to i32
   ret i32 %sext
@@ -394,17 +380,11 @@ define i32 @sexti1_i32_setcc_2(i32 %a, i32 %b) {
 
 ; Make sure we don't use th.ext instead of neg.
 define i32 @sexti1_i32_setcc_3(i32 %a, i32 %b) {
-; RV32I-LABEL: sexti1_i32_setcc_3:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    slt a0, a0, a1
-; RV32I-NEXT:    neg a0, a0
-; RV32I-NEXT:    ret
-;
-; RV32XTHEADBB-LABEL: sexti1_i32_setcc_3:
-; RV32XTHEADBB:       # %bb.0:
-; RV32XTHEADBB-NEXT:    slt a0, a0, a1
-; RV32XTHEADBB-NEXT:    neg a0, a0
-; RV32XTHEADBB-NEXT:    ret
+; CHECK-LABEL: sexti1_i32_setcc_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slt a0, a0, a1
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
   %icmp = icmp slt i32 %a, %b
   %sext = sext i1 %icmp to i32
   ret i32 %sext
@@ -477,17 +457,11 @@ define i32 @sexth_i32(i32 %a) nounwind {
 }
 
 define i32 @no_sexth_i32(i32 %a) nounwind {
-; RV32I-LABEL: no_sexth_i32:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    slli a0, a0, 17
-; RV32I-NEXT:    srai a0, a0, 16
-; RV32I-NEXT:    ret
-;
-; RV32XTHEADBB-LABEL: no_sexth_i32:
-; RV32XTHEADBB:       # %bb.0:
-; RV32XTHEADBB-NEXT:    slli a0, a0, 17
-; RV32XTHEADBB-NEXT:    srai a0, a0, 16
-; RV32XTHEADBB-NEXT:    ret
+; CHECK-LABEL: no_sexth_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 17
+; CHECK-NEXT:    srai a0, a0, 16
+; CHECK-NEXT:    ret
   %shl = shl i32 %a, 17
   %shr = ashr exact i32 %shl, 16
   ret i32 %shr
@@ -518,19 +492,12 @@ define i64 @sexth_i64(i64 %a) nounwind {
 }
 
 define i64 @no_sexth_i64(i64 %a) nounwind {
-; RV32I-LABEL: no_sexth_i64:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    slli a1, a0, 17
-; RV32I-NEXT:    srai a0, a1, 16
-; RV32I-NEXT:    srai a1, a1, 31
-; RV32I-NEXT:    ret
-;
-; RV32XTHEADBB-LABEL: no_sexth_i64:
-; RV32XTHEADBB:       # %bb.0:
-; RV32XTHEADBB-NEXT:    slli a1, a0, 17
-; RV32XTHEADBB-NEXT:    srai a0, a1, 16
-; RV32XTHEADBB-NEXT:    srai a1, a1, 31
-; RV32XTHEADBB-NEXT:    ret
+; CHECK-LABEL: no_sexth_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a1, a0, 17
+; CHECK-NEXT:    srai a0, a1, 16
+; CHECK-NEXT:    srai a1, a1, 31
+; CHECK-NEXT:    ret
   %shl = shl i64 %a, 49
   %shr = ashr exact i64 %shl, 48
   ret i64 %shr
diff --git a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
index d7c568b..24853eb 100644
--- a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
@@ -1,10 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV64I
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64I
 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadbb -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=RV64XTHEADBB,RV64XTHEADBB-NOB
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64XTHEADBB,RV64XTHEADBB-NOB
 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadbb,+b -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=RV64XTHEADBB,RV64XTHEADBB-B
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64XTHEADBB,RV64XTHEADBB-B
 
 declare i32 @llvm.ctlz.i32(i32, i1)
 
@@ -711,19 +711,12 @@ define signext i32 @sexti1_i32_2(i1 %a) nounwind {
 
 ; Make sure we don't use not+th.ext
 define zeroext i8 @sexti1_i32_setcc(i32 signext %a) {
-; RV64I-LABEL: sexti1_i32_setcc:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    srli a0, a0, 63
-; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    zext.b a0, a0
-; RV64I-NEXT:    ret
-;
-; RV64XTHEADBB-LABEL: sexti1_i32_setcc:
-; RV64XTHEADBB:       # %bb.0:
-; RV64XTHEADBB-NEXT:    srli a0, a0, 63
-; RV64XTHEADBB-NEXT:    addi a0, a0, -1
-; RV64XTHEADBB-NEXT:    zext.b a0, a0
-; RV64XTHEADBB-NEXT:    ret
+; CHECK-LABEL: sexti1_i32_setcc:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srli a0, a0, 63
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    zext.b a0, a0
+; CHECK-NEXT:    ret
   %icmp = icmp sgt i32 %a, -1
   %sext = sext i1 %icmp to i8
   ret i8 %sext
@@ -731,19 +724,12 @@ define zeroext i8 @sexti1_i32_setcc(i32 signext %a) {
 
 ; Make sure we don't use seqz+th.ext instead of snez+addi
 define signext i32 @sexti1_i32_setcc_2(i32 signext %a, i32 signext %b) {
-; RV64I-LABEL: sexti1_i32_setcc_2:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    snez a0, a0
-; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    ret
-;
-; RV64XTHEADBB-LABEL: sexti1_i32_setcc_2:
-; RV64XTHEADBB:       # %bb.0:
-; RV64XTHEADBB-NEXT:    xor a0, a0, a1
-; RV64XTHEADBB-NEXT:    snez a0, a0
-; RV64XTHEADBB-NEXT:    addi a0, a0, -1
-; RV64XTHEADBB-NEXT:    ret
+; CHECK-LABEL: sexti1_i32_setcc_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xor a0, a0, a1
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    ret
   %icmp = icmp eq i32 %a, %b
   %sext = sext i1 %icmp to i32
   ret i32 %sext
@@ -751,17 +737,11 @@ define signext i32 @sexti1_i32_setcc_2(i32 signext %a, i32 signext %b) {
 
 ; Make sure we don't use th.ext instead of neg.
 define signext i32 @sexti1_i32_setcc_3(i32 signext %a, i32 signext %b) {
-; RV64I-LABEL: sexti1_i32_setcc_3:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slt a0, a0, a1
-; RV64I-NEXT:    neg a0, a0
-; RV64I-NEXT:    ret
-;
-; RV64XTHEADBB-LABEL: sexti1_i32_setcc_3:
-; RV64XTHEADBB:       # %bb.0:
-; RV64XTHEADBB-NEXT:    slt a0, a0, a1
-; RV64XTHEADBB-NEXT:    neg a0, a0
-; RV64XTHEADBB-NEXT:    ret
+; CHECK-LABEL: sexti1_i32_setcc_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slt a0, a0, a1
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
   %icmp = icmp slt i32 %a, %b
   %sext = sext i1 %icmp to i32
   ret i32 %sext
@@ -800,19 +780,12 @@ define i64 @sexti1_i64_2(i1 %a) nounwind {
 
 ; Make sure we don't use not+th.ext
 define zeroext i8 @sexti1_i64_setcc(i64 %a) {
-; RV64I-LABEL: sexti1_i64_setcc:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    srli a0, a0, 63
-; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    zext.b a0, a0
-; RV64I-NEXT:    ret
-;
-; RV64XTHEADBB-LABEL: sexti1_i64_setcc:
-; RV64XTHEADBB:       # %bb.0:
-; RV64XTHEADBB-NEXT:    srli a0, a0, 63
-; RV64XTHEADBB-NEXT:    addi a0, a0, -1
-; RV64XTHEADBB-NEXT:    zext.b a0, a0
-; RV64XTHEADBB-NEXT:    ret
+; CHECK-LABEL: sexti1_i64_setcc:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srli a0, a0, 63
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    zext.b a0, a0
+; CHECK-NEXT:    ret
   %icmp = icmp sgt i64 %a, -1
   %sext = sext i1 %icmp to i8
   ret i8 %sext
@@ -820,19 +793,12 @@ define zeroext i8 @sexti1_i64_setcc(i64 %a) {
 
 ; Make sure we don't use seqz+th.ext instead of snez+addi
 define i64 @sexti1_i64_setcc_2(i64 %a, i64 %b) {
-; RV64I-LABEL: sexti1_i64_setcc_2:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    snez a0, a0
-; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    ret
-;
-; RV64XTHEADBB-LABEL: sexti1_i64_setcc_2:
-; RV64XTHEADBB:       # %bb.0:
-; RV64XTHEADBB-NEXT:    xor a0, a0, a1
-; RV64XTHEADBB-NEXT:    snez a0, a0
-; RV64XTHEADBB-NEXT:    addi a0, a0, -1
-; RV64XTHEADBB-NEXT:    ret
+; CHECK-LABEL: sexti1_i64_setcc_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xor a0, a0, a1
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    ret
   %icmp = icmp eq i64 %a, %b
   %sext = sext i1 %icmp to i64
   ret i64 %sext
@@ -840,17 +806,11 @@ define i64 @sexti1_i64_setcc_2(i64 %a, i64 %b) {
 
 ; Make sure we don't use th.ext instead of neg.
 define i64 @sexti1_i64_setcc_3(i64 %a, i64 %b) {
-; RV64I-LABEL: sexti1_i64_setcc_3:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slt a0, a0, a1
-; RV64I-NEXT:    neg a0, a0
-; RV64I-NEXT:    ret
-;
-; RV64XTHEADBB-LABEL: sexti1_i64_setcc_3:
-; RV64XTHEADBB:       # %bb.0:
-; RV64XTHEADBB-NEXT:    slt a0, a0, a1
-; RV64XTHEADBB-NEXT:    neg a0, a0
-; RV64XTHEADBB-NEXT:    ret
+; CHECK-LABEL: sexti1_i64_setcc_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slt a0, a0, a1
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
   %icmp = icmp slt i64 %a, %b
   %sext = sext i1 %icmp to i64
   ret i64 %sext
@@ -920,17 +880,11 @@ define signext i32 @sexth_i32(i32 signext %a) nounwind {
 }
 
 define signext i32 @no_sexth_i32(i32 signext %a) nounwind {
-; RV64I-LABEL: no_sexth_i32:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 49
-; RV64I-NEXT:    srai a0, a0, 48
-; RV64I-NEXT:    ret
-;
-; RV64XTHEADBB-LABEL: no_sexth_i32:
-; RV64XTHEADBB:       # %bb.0:
-; RV64XTHEADBB-NEXT:    slli a0, a0, 49
-; RV64XTHEADBB-NEXT:    srai a0, a0, 48
-; RV64XTHEADBB-NEXT:    ret
+; CHECK-LABEL: no_sexth_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 49
+; CHECK-NEXT:    srai a0, a0, 48
+; CHECK-NEXT:    ret
   %shl = shl i32 %a, 17
   %shr = ashr exact i32 %shl, 16
   ret i32 %shr
@@ -958,17 +912,11 @@ define i64 @sexth_i64(i64 %a) nounwind {
 }
 
 define i64 @no_sexth_i64(i64 %a) nounwind {
-; RV64I-LABEL: no_sexth_i64:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 49
-; RV64I-NEXT:    srai a0, a0, 48
-; RV64I-NEXT:    ret
-;
-; RV64XTHEADBB-LABEL: no_sexth_i64:
-; RV64XTHEADBB:       # %bb.0:
-; RV64XTHEADBB-NEXT:    slli a0, a0, 49
-; RV64XTHEADBB-NEXT:    srai a0, a0, 48
-; RV64XTHEADBB-NEXT:    ret
+; CHECK-LABEL: no_sexth_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 49
+; CHECK-NEXT:    srai a0, a0, 48
+; CHECK-NEXT:    ret
   %shl = shl i64 %a, 49
   %shr = ashr exact i64 %shl, 48
   ret i64 %shr
@@ -1067,15 +1015,10 @@ define i64 @zext_bf2_i64(i64 %a) nounwind {
 }
 
 define i64 @zext_i64_srliw(i64 %a) nounwind {
-; RV64I-LABEL: zext_i64_srliw:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    srliw a0, a0, 16
-; RV64I-NEXT:    ret
-;
-; RV64XTHEADBB-LABEL: zext_i64_srliw:
-; RV64XTHEADBB:       # %bb.0:
-; RV64XTHEADBB-NEXT:    srliw a0, a0, 16
-; RV64XTHEADBB-NEXT:    ret
+; CHECK-LABEL: zext_i64_srliw:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srliw a0, a0, 16
+; CHECK-NEXT:    ret
   %1 = lshr i64 %a, 16
   %and = and i64 %1, 65535
   ret i64 %and
diff --git a/llvm/test/CodeGen/RISCV/xqcibm-extract.ll b/llvm/test/CodeGen/RISCV/xqcibm-extract.ll
index c2c9d07..34657ba 100644
--- a/llvm/test/CodeGen/RISCV/xqcibm-extract.ll
+++ b/llvm/test/CodeGen/RISCV/xqcibm-extract.ll
@@ -1,10 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=RV32I
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=RV32XQCIBM
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32XQCIBM
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm,+zbb -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=RV32XQCIBMZBB
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32XQCIBMZBB
 
 define i32 @sexti1_i32(i1 %a) nounwind {
 ; RV32I-LABEL: sexti1_i32:
@@ -76,26 +76,12 @@ define zeroext i8 @sexti1_i32_setcc(i32 signext %a) {
 
 ; Make sure we don't use seqz+qc.ext instead of snez+addi
 define i32 @sexti1_i32_setcc_2(i32 %a, i32 %b) {
-; RV32I-LABEL: sexti1_i32_setcc_2:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    snez a0, a0
-; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    ret
-;
-; RV32XQCIBM-LABEL: sexti1_i32_setcc_2:
-; RV32XQCIBM:       # %bb.0:
-; RV32XQCIBM-NEXT:    xor a0, a0, a1
-; RV32XQCIBM-NEXT:    snez a0, a0
-; RV32XQCIBM-NEXT:    addi a0, a0, -1
-; RV32XQCIBM-NEXT:    ret
-;
-; RV32XQCIBMZBB-LABEL: sexti1_i32_setcc_2:
-; RV32XQCIBMZBB:       # %bb.0:
-; RV32XQCIBMZBB-NEXT:    xor a0, a0, a1
-; RV32XQCIBMZBB-NEXT:    snez a0, a0
-; RV32XQCIBMZBB-NEXT:    addi a0, a0, -1
-; RV32XQCIBMZBB-NEXT:    ret
+; CHECK-LABEL: sexti1_i32_setcc_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xor a0, a0, a1
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    ret
   %icmp = icmp eq i32 %a, %b
   %sext = sext i1 %icmp to i32
   ret i32 %sext
@@ -103,23 +89,11 @@ define i32 @sexti1_i32_setcc_2(i32 %a, i32 %b) {
 
 ; Make sure we don't use qc.ext instead of neg.
 define i32 @sexti1_i32_setcc_3(i32 %a, i32 %b) {
-; RV32I-LABEL: sexti1_i32_setcc_3:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    slt a0, a0, a1
-; RV32I-NEXT:    neg a0, a0
-; RV32I-NEXT:    ret
-;
-; RV32XQCIBM-LABEL: sexti1_i32_setcc_3:
-; RV32XQCIBM:       # %bb.0:
-; RV32XQCIBM-NEXT:    slt a0, a0, a1
-; RV32XQCIBM-NEXT:    neg a0, a0
-; RV32XQCIBM-NEXT:    ret
-;
-; RV32XQCIBMZBB-LABEL: sexti1_i32_setcc_3:
-; RV32XQCIBMZBB:       # %bb.0:
-; RV32XQCIBMZBB-NEXT:    slt a0, a0, a1
-; RV32XQCIBMZBB-NEXT:    neg a0, a0
-; RV32XQCIBMZBB-NEXT:    ret
+; CHECK-LABEL: sexti1_i32_setcc_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slt a0, a0, a1
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
   %icmp = icmp slt i32 %a, %b
   %sext = sext i1 %icmp to i32
   ret i32 %sext
@@ -349,40 +323,20 @@ define i64 @sexti16_i64_2(i16 %a) {
 }
 
 define i64 @sexti32_i64(i64 %a) {
-; RV32I-LABEL: sexti32_i64:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    srai a1, a0, 31
-; RV32I-NEXT:    ret
-;
-; RV32XQCIBM-LABEL: sexti32_i64:
-; RV32XQCIBM:       # %bb.0:
-; RV32XQCIBM-NEXT:    srai a1, a0, 31
-; RV32XQCIBM-NEXT:    ret
-;
-; RV32XQCIBMZBB-LABEL: sexti32_i64:
-; RV32XQCIBMZBB:       # %bb.0:
-; RV32XQCIBMZBB-NEXT:    srai a1, a0, 31
-; RV32XQCIBMZBB-NEXT:    ret
+; CHECK-LABEL: sexti32_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srai a1, a0, 31
+; CHECK-NEXT:    ret
   %shl = shl i64 %a, 32
   %shr = ashr exact i64 %shl, 32
   ret i64 %shr
 }
 
 define i64 @sexti32_i64_2(i32 %a) {
-; RV32I-LABEL: sexti32_i64_2:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    srai a1, a0, 31
-; RV32I-NEXT:    ret
-;
-; RV32XQCIBM-LABEL: sexti32_i64_2:
-; RV32XQCIBM:       # %bb.0:
-; RV32XQCIBM-NEXT:    srai a1, a0, 31
-; RV32XQCIBM-NEXT:    ret
-;
-; RV32XQCIBMZBB-LABEL: sexti32_i64_2:
-; RV32XQCIBMZBB:       # %bb.0:
-; RV32XQCIBMZBB-NEXT:    srai a1, a0, 31
-; RV32XQCIBMZBB-NEXT:    ret
+; CHECK-LABEL: sexti32_i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srai a1, a0, 31
+; CHECK-NEXT:    ret
   %1 = sext i32 %a to i64
   ret i64 %1
 }
@@ -408,20 +362,10 @@ define i32 @extu_from_and_i32(i32 %x) {
 }
 
 define i32 @no_extu_from_and_i32(i32 %x) {
-; RV32I-LABEL: no_extu_from_and_i32:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a0, a0, 31
-; RV32I-NEXT:    ret
-;
-; RV32XQCIBM-LABEL: no_extu_from_and_i32:
-; RV32XQCIBM:       # %bb.0:
-; RV32XQCIBM-NEXT:    andi a0, a0, 31
-; RV32XQCIBM-NEXT:    ret
-;
-; RV32XQCIBMZBB-LABEL: no_extu_from_and_i32:
-; RV32XQCIBMZBB:       # %bb.0:
-; RV32XQCIBMZBB-NEXT:    andi a0, a0, 31
-; RV32XQCIBMZBB-NEXT:    ret
+; CHECK-LABEL: no_extu_from_and_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 31
+; CHECK-NEXT:    ret
   %a = and i32 %x, 31
   ret i32 %a
 }