[AggressiveInstCombine] Add test for shifts from or chains. NFC

2 files changed, 199 insertions, 0 deletions

diff --git a/llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll b/llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
index 0e3fe56..cbe3c13 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
@@ -2480,3 +2480,55 @@ define void @bitcast_gep(ptr %p, ptr %dest) {
   store i32 %trunc, ptr %dest, align 4
   ret void
 }
+
+define i1 @loadCombine_4consecutive_rev_icmp0(ptr %p) {
+; LE-LABEL: @loadCombine_4consecutive_rev_icmp0(
+; LE-NEXT:    [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
+; LE-NEXT:    [[C:%.*]] = icmp eq i32 [[L1]], 0
+; LE-NEXT:    ret i1 [[C]]
+;
+; BE-LABEL: @loadCombine_4consecutive_rev_icmp0(
+; BE-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
+; BE-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; BE-NEXT:    [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; BE-NEXT:    [[L1:%.*]] = load i8, ptr [[P]], align 1
+; BE-NEXT:    [[L2:%.*]] = load i8, ptr [[P1]], align 1
+; BE-NEXT:    [[L3:%.*]] = load i8, ptr [[P2]], align 1
+; BE-NEXT:    [[L4:%.*]] = load i8, ptr [[P3]], align 1
+; BE-NEXT:    [[E1:%.*]] = zext i8 [[L1]] to i32
+; BE-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i32
+; BE-NEXT:    [[E3:%.*]] = zext i8 [[L3]] to i32
+; BE-NEXT:    [[E4:%.*]] = zext i8 [[L4]] to i32
+; BE-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 8
+; BE-NEXT:    [[S3:%.*]] = shl i32 [[E3]], 16
+; BE-NEXT:    [[S4:%.*]] = shl i32 [[E4]], 24
+; BE-NEXT:    [[O1:%.*]] = or i32 [[S4]], [[S3]]
+; BE-NEXT:    [[O2:%.*]] = or i32 [[O1]], [[S2]]
+; BE-NEXT:    [[O3:%.*]] = or i32 [[O2]], [[E1]]
+; BE-NEXT:    [[C:%.*]] = icmp eq i32 [[O3]], 0
+; BE-NEXT:    ret i1 [[C]]
+;
+  %p1 = getelementptr i8, ptr %p, i32 1
+  %p2 = getelementptr i8, ptr %p, i32 2
+  %p3 = getelementptr i8, ptr %p, i32 3
+  %l1 = load i8, ptr %p
+  %l2 = load i8, ptr %p1
+  %l3 = load i8, ptr %p2
+  %l4 = load i8, ptr %p3
+
+  %e1 = zext i8 %l1 to i32
+  %e2 = zext i8 %l2 to i32
+  %e3 = zext i8 %l3 to i32
+  %e4 = zext i8 %l4 to i32
+
+  %s2 = shl i32 %e2, 8
+  %s3 = shl i32 %e3, 16
+  %s4 = shl i32 %e4, 24
+
+  %o1 = or i32 %s4, %s3
+  %o2 = or i32 %o1, %s2
+  %o3 = or i32 %o2, %e1
+
+  %c = icmp eq i32 %o3, 0
+  ret i1 %c
+}
diff --git a/llvm/test/Transforms/AggressiveInstCombine/or-shift-chain.ll b/llvm/test/Transforms/AggressiveInstCombine/or-shift-chain.ll
new file mode 100644
index 0000000..6816ccc
--- /dev/null
+++ b/llvm/test/Transforms/AggressiveInstCombine/or-shift-chain.ll
@@ -0,0 +1,147 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=aggressive-instcombine -S | FileCheck %s
+
+define i1 @remove_shift_nuw_ab(i8 %a, i8 %b, i8 %s) {
+; CHECK-LABEL: @remove_shift_nuw_ab(
+; CHECK-NEXT:    [[T:%.*]] = shl nuw i8 [[A:%.*]], [[S:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = or i8 [[T]], [[B:%.*]]
+; CHECK-NEXT:    [[IC:%.*]] = icmp eq i8 [[OR]], 0
+; CHECK-NEXT:    ret i1 [[IC]]
+;
+  %t = shl nuw i8 %a, %s
+  %or = or i8 %t, %b
+  %ic = icmp eq i8 %or, 0
+  ret i1 %ic
+}
+
+define i1 @remove_shift_nuw_ba(i8 %a, i8 %b, i8 %s) {
+; CHECK-LABEL: @remove_shift_nuw_ba(
+; CHECK-NEXT:    [[T:%.*]] = shl nuw i8 [[A:%.*]], [[S:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = or i8 [[B:%.*]], [[T]]
+; CHECK-NEXT:    [[IC:%.*]] = icmp eq i8 [[OR]], 0
+; CHECK-NEXT:    ret i1 [[IC]]
+;
+  %t = shl nuw i8 %a, %s
+  %or = or i8 %b, %t
+  %ic = icmp eq i8 %or, 0
+  ret i1 %ic
+}
+
+define i1 @remove_shift_nsw(i8 %a, i8 %b, i8 %s) {
+; CHECK-LABEL: @remove_shift_nsw(
+; CHECK-NEXT:    [[T:%.*]] = shl nsw i8 [[A:%.*]], [[S:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = or i8 [[T]], [[B:%.*]]
+; CHECK-NEXT:    [[IC:%.*]] = icmp eq i8 [[OR]], 0
+; CHECK-NEXT:    ret i1 [[IC]]
+;
+  %t = shl nsw i8 %a, %s
+  %or = or i8 %t, %b
+  %ic = icmp eq i8 %or, 0
+  ret i1 %ic
+}
+
+define i1 @remove_shift_nuw_ne(i8 %a, i8 %b, i8 %s) {
+; CHECK-LABEL: @remove_shift_nuw_ne(
+; CHECK-NEXT:    [[T:%.*]] = shl nuw i8 [[A:%.*]], [[S:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = or i8 [[T]], [[B:%.*]]
+; CHECK-NEXT:    [[IC:%.*]] = icmp eq i8 [[OR]], 0
+; CHECK-NEXT:    ret i1 [[IC]]
+;
+  %t = shl nuw i8 %a, %s
+  %or = or i8 %t, %b
+  %ic = icmp eq i8 %or, 0
+  ret i1 %ic
+}
+
+define i1 @remove_shift_nsw_ne(i8 %a, i8 %b, i8 %s) {
+; CHECK-LABEL: @remove_shift_nsw_ne(
+; CHECK-NEXT:    [[T:%.*]] = shl nsw i8 [[A:%.*]], [[S:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = or i8 [[T]], [[B:%.*]]
+; CHECK-NEXT:    [[IC:%.*]] = icmp eq i8 [[OR]], 0
+; CHECK-NEXT:    ret i1 [[IC]]
+;
+  %t = shl nsw i8 %a, %s
+  %or = or i8 %t, %b
+  %ic = icmp eq i8 %or, 0
+  ret i1 %ic
+}
+
+define i1 @remove_shift_wraps(i8 %a, i8 %b, i8 %s) {
+; CHECK-LABEL: @remove_shift_wraps(
+; CHECK-NEXT:    [[T:%.*]] = shl i8 [[A:%.*]], [[S:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = or i8 [[T]], [[B:%.*]]
+; CHECK-NEXT:    [[IC:%.*]] = icmp eq i8 [[OR]], 0
+; CHECK-NEXT:    ret i1 [[IC]]
+;
+  %t = shl i8 %a, %s
+  %or = or i8 %t, %b
+  %ic = icmp eq i8 %or, 0
+  ret i1 %ic
+}
+
+define i1 @remove_shift_chain_d(i8 %a, i8 %b, i8 %c, i8 %d, i8 %s) {
+; CHECK-LABEL: @remove_shift_chain_d(
+; CHECK-NEXT:    [[DT:%.*]] = shl nuw i8 [[D:%.*]], [[S:%.*]]
+; CHECK-NEXT:    [[OR1:%.*]] = or i8 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[OR2:%.*]] = or i8 [[C:%.*]], [[DT]]
+; CHECK-NEXT:    [[OR:%.*]] = or i8 [[OR1]], [[OR2]]
+; CHECK-NEXT:    [[IC:%.*]] = icmp eq i8 [[OR]], 0
+; CHECK-NEXT:    ret i1 [[IC]]
+;
+  %dt = shl nuw i8 %d, %s
+  %or1 = or i8 %a, %b
+  %or2 = or i8 %c, %dt
+  %or = or i8 %or1, %or2
+  %ic = icmp eq i8 %or, 0
+  ret i1 %ic
+}
+
+define i1 @remove_shift_chain_abcd(i8 %a, i8 %b, i8 %c, i8 %d, i8 %s) {
+; CHECK-LABEL: @remove_shift_chain_abcd(
+; CHECK-NEXT:    [[AT:%.*]] = shl nuw i8 [[A:%.*]], [[S:%.*]]
+; CHECK-NEXT:    [[BT:%.*]] = shl nuw i8 [[B:%.*]], 2
+; CHECK-NEXT:    [[CT:%.*]] = shl nuw i8 [[C:%.*]], 1
+; CHECK-NEXT:    [[DT:%.*]] = shl nuw i8 [[D:%.*]], [[S]]
+; CHECK-NEXT:    [[OR1:%.*]] = or i8 [[AT]], [[BT]]
+; CHECK-NEXT:    [[OR2:%.*]] = or i8 [[CT]], [[DT]]
+; CHECK-NEXT:    [[OR:%.*]] = or i8 [[OR1]], [[OR2]]
+; CHECK-NEXT:    [[IC:%.*]] = icmp eq i8 [[OR]], 0
+; CHECK-NEXT:    ret i1 [[IC]]
+;
+  %at = shl nuw i8 %a, %s
+  %bt = shl nuw i8 %b, 2
+  %ct = shl nuw i8 %c, 1
+  %dt = shl nuw i8 %d, %s
+  %or1 = or i8 %at, %bt
+  %or2 = or i8 %ct, %dt
+  %or = or i8 %or1, %or2
+  %ic = icmp eq i8 %or, 0
+  ret i1 %ic
+}
+
+define i1 @remove_shift_chain_abcd_multiuse(i8 %a, i8 %b, i8 %c, i8 %d, i8 %s) {
+; CHECK-LABEL: @remove_shift_chain_abcd_multiuse(
+; CHECK-NEXT:    [[AT:%.*]] = shl nuw i8 [[A:%.*]], [[S:%.*]]
+; CHECK-NEXT:    [[BT:%.*]] = shl nuw i8 [[B:%.*]], 2
+; CHECK-NEXT:    [[CT:%.*]] = shl nuw i8 [[C:%.*]], 1
+; CHECK-NEXT:    [[DT:%.*]] = shl nuw i8 [[D:%.*]], [[S]]
+; CHECK-NEXT:    [[OR1:%.*]] = or i8 [[AT]], [[BT]]
+; CHECK-NEXT:    [[OR2:%.*]] = or i8 [[CT]], [[DT]]
+; CHECK-NEXT:    [[OR:%.*]] = or i8 [[OR1]], [[OR2]]
+; CHECK-NEXT:    [[IC:%.*]] = icmp eq i8 [[OR]], 0
+; CHECK-NEXT:    call void @use(i8 [[OR]])
+; CHECK-NEXT:    ret i1 [[IC]]
+;
+  %at = shl nuw i8 %a, %s
+  %bt = shl nuw i8 %b, 2
+  %ct = shl nuw i8 %c, 1
+  %dt = shl nuw i8 %d, %s
+  %or1 = or i8 %at, %bt
+  %or2 = or i8 %ct, %dt
+  %or = or i8 %or1, %or2
+  %ic = icmp eq i8 %or, 0
+  call void @use(i8 %or)
+  ret i1 %ic
+}
+
+declare void @use(i8)