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| author | Craig Topper <craig.topper@intel.com> | 2020-07-04 14:35:49 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2020-07-04 14:35:49 -0700 |
| commit | 76123d338dc542d25cc9c4f20ddc49df1b9712cd (patch) | |
| tree | 9ab3819eca03d39c8a324d8ceed3dc174fcc237d | |
| parent | 6c4a5e9257bac022ffe60e466686ba7fc96ffd1a (diff) | |
| download | llvm-76123d338dc542d25cc9c4f20ddc49df1b9712cd.zip llvm-76123d338dc542d25cc9c4f20ddc49df1b9712cd.tar.gz llvm-76123d338dc542d25cc9c4f20ddc49df1b9712cd.tar.bz2 | |
[DAGCombiner] visitSIGN_EXTEND_INREG should fold sext_vector_inreg(undef) to 0 not undef.
We need to ensure that the sign bits of the result all match
so we can't fold to undef.
Similar to PR46585.
Reviewed By: lebedev.ri
Differential Revision: https://reviews.llvm.org/D83163
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index c0d5337..015d78a3 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -10957,8 +10957,9 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { unsigned VTBits = VT.getScalarSizeInBits(); unsigned ExtVTBits = ExtVT.getScalarSizeInBits(); + // sext_vector_inreg(undef) = 0 because the top bit will all be the same. if (N0.isUndef()) - return DAG.getUNDEF(VT); + return DAG.getConstant(0, SDLoc(N), VT); // fold (sext_in_reg c1) -> c1 if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) |