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authorPaul Walker <paul.walker@arm.com>2020-07-04 09:17:53 +0000
committerPaul Walker <paul.walker@arm.com>2020-07-04 09:21:40 +0000
commit7356b4243ad9dc373c63bb4b7ac0ba4f877c47ee (patch)
tree1a1769ed682b968dc25611f646f79ff3d657e8fe
parent15a60fe09f4618a7fb451f37aebfd1a671f83713 (diff)
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[SVE] Fix invalid assert in expand_DestructiveOp.
AArch64ExpandPseudo::expand_DestructiveOp contains an assert to ensure the destructive operand's register is unique. However, this is only required when psuedo expansion emits a movprfx. A simple example when a movprfx is not required is Z0 = FADD_ZPZZ_UNDEF_S P0, Z0, Z0 which expands to an unprefixed FADD_ZPmZ_S instruction. This patch moves the assert to the places where a movprfx is emitted. Differential Revision: https://reviews.llvm.org/D83029
-rw-r--r--llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp8
-rw-r--r--llvm/test/CodeGen/AArch64/sve-pseudos-expand-undef.mir22
2 files changed, 28 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index 2058764..9e65ad2 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -438,8 +438,6 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
DOPRegIsUnique = true;
break;
}
-
- assert (DOPRegIsUnique && "The destructive operand should be unique");
#endif
// Resolve the reverse opcode
@@ -483,6 +481,9 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
//
MachineInstrBuilder PRFX, DOP;
if (FalseZero) {
+#ifndef NDEBUG
+ assert(DOPRegIsUnique && "The destructive operand should be unique");
+#endif
assert(ElementSize != AArch64::ElementSizeNone &&
"This instruction is unpredicated");
@@ -495,6 +496,9 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
// After the movprfx, the destructive operand is same as Dst
DOPIdx = 0;
} else if (DstReg != MI.getOperand(DOPIdx).getReg()) {
+#ifndef NDEBUG
+ assert(DOPRegIsUnique && "The destructive operand should be unique");
+#endif
PRFX = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(MovPrfx))
.addReg(DstReg, RegState::Define)
.addReg(MI.getOperand(DOPIdx).getReg());
diff --git a/llvm/test/CodeGen/AArch64/sve-pseudos-expand-undef.mir b/llvm/test/CodeGen/AArch64/sve-pseudos-expand-undef.mir
new file mode 100644
index 0000000..c81363f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-pseudos-expand-undef.mir
@@ -0,0 +1,22 @@
+# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=aarch64-expand-pseudo -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+---
+name: add_x
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$p0' }
+ - { reg: '$z0' }
+frameInfo:
+ maxCallFrameSize: 0
+body: |
+ bb.0:
+ liveins: $p0, $z0
+
+ ; CHECK: add_x
+ ; CHECK-NOT: MOVPRFX
+ ; CHECK: $z0 = FADD_ZPmZ_S renamable $p0, killed $z0, renamable $z0
+ ; CHECK-NEXT: RET
+ renamable $z0 = FADD_ZPZZ_UNDEF_S renamable $p0, renamable $z0, killed renamable $z0
+ RET_ReallyLR
+
+...