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| author | Sanjay Patel <spatel@rotateright.com> | 2020-06-25 15:43:40 -0400 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2020-06-25 16:28:10 -0400 |
| commit | 723129583090e7f7b5f4626a0ab06a0b64ad6fdf (patch) | |
| tree | a9149e8ffd0b859aea0af5242b0fe43483c301ef | |
| parent | b5769a777f1c146e5457200fe52fa2041e182da4 (diff) | |
| download | llvm-723129583090e7f7b5f4626a0ab06a0b64ad6fdf.zip llvm-723129583090e7f7b5f4626a0ab06a0b64ad6fdf.tar.gz llvm-723129583090e7f7b5f4626a0ab06a0b64ad6fdf.tar.bz2 | |
[x86] add vector test for merged condition branching; NFC
| -rw-r--r-- | llvm/test/CodeGen/X86/setcc-logic.ll | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/setcc-logic.ll b/llvm/test/CodeGen/X86/setcc-logic.ll index 46db927..a878a33 100644 --- a/llvm/test/CodeGen/X86/setcc-logic.ll +++ b/llvm/test/CodeGen/X86/setcc-logic.ll @@ -315,6 +315,36 @@ return: ret i32 192 } +; PR44565 - https://bugs.llvm.org/show_bug.cgi?id=44565 + +define i32 @vec_extract_branch(<2 x double> %x) { +; CHECK-LABEL: vec_extract_branch: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: cmpltpd %xmm0, %xmm1 +; CHECK-NEXT: movmskpd %xmm1, %eax +; CHECK-NEXT: testb $1, %al +; CHECK-NEXT: je .LBB16_3 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: shrb %al +; CHECK-NEXT: je .LBB16_3 +; CHECK-NEXT: # %bb.2: # %true +; CHECK-NEXT: movl $42, %eax +; CHECK-NEXT: retq +; CHECK-NEXT: .LBB16_3: # %false +; CHECK-NEXT: movl $88, %eax +; CHECK-NEXT: retq + %t1 = fcmp ogt <2 x double> %x, zeroinitializer + %t2 = extractelement <2 x i1> %t1, i32 0 + %t3 = extractelement <2 x i1> %t1, i32 1 + %t4 = and i1 %t2, %t3 + br i1 %t4, label %true, label %false +true: + ret i32 42 +false: + ret i32 88 +} + define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) nounwind { ; CHECK-LABEL: all_bits_clear_vec: ; CHECK: # %bb.0: |