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| author | Krzysztof Parzyszek <kparzysz@quicinc.com> | 2020-12-15 15:59:59 -0600 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@quicinc.com> | 2020-12-15 16:01:24 -0600 |
| commit | 71601d2ac9954cb59c443cb3ae442cb106df35d4 (patch) | |
| tree | 6f50e90d4f8c3163f2feaf3a2ff749e9e600674e | |
| parent | e7e7d371fd871c9976bd2c7bbb9be60fe37c6d28 (diff) | |
| download | llvm-71601d2ac9954cb59c443cb3ae442cb106df35d4.zip llvm-71601d2ac9954cb59c443cb3ae442cb106df35d4.tar.gz llvm-71601d2ac9954cb59c443cb3ae442cb106df35d4.tar.bz2 | |
[Hexagon] Fix bitcasting v1i8 -> i8
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/isel-bitcast-v1i8-i8.ll | 22 |
2 files changed, 28 insertions, 4 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index b60758a..c8994a3 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -3151,10 +3151,12 @@ HexagonTargetLowering::ReplaceNodeResults(SDNode *N, case ISD::BITCAST: // Handle a bitcast from v8i1 to i8. if (N->getValueType(0) == MVT::i8) { - SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, - N->getOperand(0), DAG); - SDValue T = DAG.getAnyExtOrTrunc(P, dl, MVT::i8); - Results.push_back(T); + if (N->getOperand(0).getValueType() == MVT::v8i1) { + SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, + N->getOperand(0), DAG); + SDValue T = DAG.getAnyExtOrTrunc(P, dl, MVT::i8); + Results.push_back(T); + } } break; } diff --git a/llvm/test/CodeGen/Hexagon/isel-bitcast-v1i8-i8.ll b/llvm/test/CodeGen/Hexagon/isel-bitcast-v1i8-i8.ll new file mode 100644 index 0000000..77696a3 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/isel-bitcast-v1i8-i8.ll @@ -0,0 +1,22 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -march=hexagon < %s | FileCheck %s + +; This shouldn't crash. + +define i8 @fred(<4 x i8>* %a0) #0 { +; CHECK-LABEL: fred: +; CHECK: // %bb.0: +; CHECK-NEXT: { +; CHECK-NEXT: r0 = memw(r0+#0) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r0 = extractu(r0,#8,#16) +; CHECK-NEXT: jumpr r31 +; CHECK-NEXT: } + %v0 = load <4 x i8>, <4 x i8>* %a0, align 4 + %v1 = shufflevector <4 x i8> %v0, <4 x i8> undef, <1 x i32> <i32 2> + %v2 = bitcast <1 x i8> %v1 to i8 + ret i8 %v2 +} + +attributes #0 = { nounwind "target-cpu"="hexagonv66" } |