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authorMatt Arsenault <Matthew.Arsenault@amd.com>2025-09-05 12:52:00 +0900
committerGitHub <noreply@github.com>2025-09-05 12:52:00 +0900
commit68f8e6e9945285ddd05b31c5528a29e3f09a507c (patch)
treed2e7e63f7d39448fe4ced523daae9d7dea2c89ff
parent7fb1dc08d2f025aad5777bb779dfac1197e9ef87 (diff)
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AMDGPU: Use switch to implement getRegPressureSetLimit (#156993)
-rw-r--r--llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp9
1 files changed, 5 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index a1fcf26..2248838 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3756,14 +3756,15 @@ unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
unsigned SIRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF,
unsigned Idx) const {
- if (Idx == AMDGPU::RegisterPressureSets::VGPR_32 ||
- Idx == AMDGPU::RegisterPressureSets::AGPR_32)
+ switch (static_cast<AMDGPU::RegisterPressureSets>(Idx)) {
+ case AMDGPU::RegisterPressureSets::VGPR_32:
+ case AMDGPU::RegisterPressureSets::AGPR_32:
return getRegPressureLimit(&AMDGPU::VGPR_32RegClass,
const_cast<MachineFunction &>(MF));
-
- if (Idx == AMDGPU::RegisterPressureSets::SReg_32)
+ case AMDGPU::RegisterPressureSets::SReg_32:
return getRegPressureLimit(&AMDGPU::SGPR_32RegClass,
const_cast<MachineFunction &>(MF));
+ }
llvm_unreachable("Unexpected register pressure set!");
}