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| author | Dmitry Vassiliev <dvassiliev@accesssoftek.com> | 2022-02-15 01:23:11 +0300 |
|---|---|---|
| committer | Dmitry Vassiliev <dvassiliev@accesssoftek.com> | 2022-02-15 01:23:11 +0300 |
| commit | 6645bfa8f501fd7698ce584976bea9c99c49d64d (patch) | |
| tree | d180c39b0398a41dcd7e3e8e328db05dc9b66556 | |
| parent | 37f422f4ac31c8b8041c6b62065263314282dab6 (diff) | |
| download | llvm-6645bfa8f501fd7698ce584976bea9c99c49d64d.zip llvm-6645bfa8f501fd7698ce584976bea9c99c49d64d.tar.gz llvm-6645bfa8f501fd7698ce584976bea9c99c49d64d.tar.bz2 | |
[NVPTX] Fix bug with int_nvvm_rotate_b64 when operand immediate
Need to subract from 64, not 32.
Reviewed By: tra
Differential Revision: https://reviews.llvm.org/D119639
| -rw-r--r-- | llvm/lib/Target/NVPTX/NVPTXIntrinsics.td | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/NVPTX/rotate_64.ll | 25 |
2 files changed, 26 insertions, 1 deletions
diff --git a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td index ec069a0..479b014 100644 --- a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td +++ b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td @@ -2473,7 +2473,7 @@ def : Pat<(int_nvvm_rotate_right_b64 Int64Regs:$src, Int32Regs:$amt), // SW version of rotate 64 def : Pat<(int_nvvm_rotate_b64 Int64Regs:$src, (i32 imm:$amt)), - (ROT64imm_sw Int64Regs:$src, imm:$amt, (SUB_FRM_32 node:$amt))>, + (ROT64imm_sw Int64Regs:$src, imm:$amt, (SUB_FRM_64 node:$amt))>, Requires<[noHWROT32]>; def : Pat<(int_nvvm_rotate_b64 Int64Regs:$src, Int32Regs:$amt), (ROTL64reg_sw Int64Regs:$src, Int32Regs:$amt)>, diff --git a/llvm/test/CodeGen/NVPTX/rotate_64.ll b/llvm/test/CodeGen/NVPTX/rotate_64.ll new file mode 100644 index 0000000..1ba0dfa --- /dev/null +++ b/llvm/test/CodeGen/NVPTX/rotate_64.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -march=nvptx | FileCheck %s + + +declare i64 @llvm.nvvm.rotate.b64(i64, i32) +declare i64 @llvm.nvvm.rotate.right.b64(i64, i32) + +; CHECK: rotate64 +define i64 @rotate64(i64 %a, i32 %b) { +; CHECK: shl.b64 [[LHS:%.*]], [[RD1:%.*]], 3; +; CHECK: shr.b64 [[RHS:%.*]], [[RD1]], 61; +; CHECK: add.u64 [[RD2:%.*]], [[LHS]], [[RHS]]; +; CHECK: ret + %val = tail call i64 @llvm.nvvm.rotate.b64(i64 %a, i32 3) + ret i64 %val +} + +; CHECK: rotateright64 +define i64 @rotateright64(i64 %a, i32 %b) { +; CHECK: shl.b64 [[LHS:%.*]], [[RD1:%.*]], 61; +; CHECK: shr.b64 [[RHS:%.*]], [[RD1]], 3; +; CHECK: add.u64 [[RD2:%.*]], [[LHS]], [[RHS]]; +; CHECK: ret + %val = tail call i64 @llvm.nvvm.rotate.right.b64(i64 %a, i32 3) + ret i64 %val +} |