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author | Kazu Hirata <kazu@google.com> | 2021-02-03 20:41:18 -0800 |
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committer | Kazu Hirata <kazu@google.com> | 2021-02-03 20:41:18 -0800 |
commit | 643c00f717a2cc20a85cdbfa3681e8f61af8c64f (patch) | |
tree | 506d1d12f4b37644fc5d4cbc9feb2d7c419580b3 | |
parent | b4de30f6afe446a38c30626e611daa5509f19b92 (diff) | |
download | llvm-643c00f717a2cc20a85cdbfa3681e8f61af8c64f.zip llvm-643c00f717a2cc20a85cdbfa3681e8f61af8c64f.tar.gz llvm-643c00f717a2cc20a85cdbfa3681e8f61af8c64f.tar.bz2 |
[TableGen] Use ListSeparator (NFC)
-rw-r--r-- | llvm/utils/TableGen/CodeGenSchedule.cpp | 21 |
1 files changed, 7 insertions, 14 deletions
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp index b20eb6ef..14d0ee6 100644 --- a/llvm/utils/TableGen/CodeGenSchedule.cpp +++ b/llvm/utils/TableGen/CodeGenSchedule.cpp @@ -2262,25 +2262,18 @@ void PredTransitions::dump() const { for (std::vector<PredTransition>::const_iterator TI = TransVec.begin(), TE = TransVec.end(); TI != TE; ++TI) { dbgs() << "{"; - for (SmallVectorImpl<PredCheck>::const_iterator - PCI = TI->PredTerm.begin(), PCE = TI->PredTerm.end(); - PCI != PCE; ++PCI) { - if (PCI != TI->PredTerm.begin()) - dbgs() << ", "; - dbgs() << SchedModels.getSchedRW(PCI->RWIdx, PCI->IsRead).Name - << ":" << PCI->Predicate->getName(); - } + ListSeparator LS; + for (const PredCheck &PC : TI->PredTerm) + dbgs() << LS << SchedModels.getSchedRW(PC.RWIdx, PC.IsRead).Name << ":" + << PC.Predicate->getName(); dbgs() << "},\n => {"; for (SmallVectorImpl<SmallVector<unsigned,4>>::const_iterator WSI = TI->WriteSequences.begin(), WSE = TI->WriteSequences.end(); WSI != WSE; ++WSI) { dbgs() << "("; - for (SmallVectorImpl<unsigned>::const_iterator - WI = WSI->begin(), WE = WSI->end(); WI != WE; ++WI) { - if (WI != WSI->begin()) - dbgs() << ", "; - dbgs() << SchedModels.getSchedWrite(*WI).Name; - } + ListSeparator LS; + for (unsigned N : *WSI) + dbgs() << LS << SchedModels.getSchedWrite(N).Name; dbgs() << "),"; } dbgs() << "}\n"; |