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| author | Craig Topper <craig.topper@sifive.com> | 2024-07-05 19:34:19 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-07-05 19:34:19 -0700 |
| commit | 6337fdcc520e8f948bef23b361c75edeb32ed015 (patch) | |
| tree | 837c13dd594caba67c76a1b07db200a9caac417c | |
| parent | be26e545424a6e006cd67e4433c88c25b23404ae (diff) | |
| download | llvm-6337fdcc520e8f948bef23b361c75edeb32ed015.zip llvm-6337fdcc520e8f948bef23b361c75edeb32ed015.tar.gz llvm-6337fdcc520e8f948bef23b361c75edeb32ed015.tar.bz2 | |
[RISCV] Use EXTLOAD in lowerVECTOR_SHUFFLE. (#97862)
We're creating a load and a splat. The splat doesn't use the extended
bits so it doesn't matter what extend we use.
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 9a4d77d..1e37f2c 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -5050,7 +5050,7 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, Ld->getOriginalAlign(), Ld->getMemOperand()->getFlags()); else - V = DAG.getExtLoad(ISD::SEXTLOAD, DL, XLenVT, Ld->getChain(), NewAddr, + V = DAG.getExtLoad(ISD::EXTLOAD, DL, XLenVT, Ld->getChain(), NewAddr, Ld->getPointerInfo().getWithOffset(Offset), SVT, Ld->getOriginalAlign(), Ld->getMemOperand()->getFlags()); diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll index 28ce6a1..f67282f9e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll @@ -5863,7 +5863,7 @@ define i8 @vreduce_mul_v2i8(ptr %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: lb a0, 1(a0) +; CHECK-NEXT: lbu a0, 1(a0) ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret |