diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2024-12-19 17:55:19 +0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-12-19 17:55:19 +0700 |
| commit | 5fb8d70e5f1c5d26bfa6ca9034863c10f3d8669d (patch) | |
| tree | ca60dfe062a72e23f333536fea315d29dc21eefc | |
| parent | 5a3f1acad7e8ce0e8cb90165794dce71f4b80bcd (diff) | |
| download | llvm-5fb8d70e5f1c5d26bfa6ca9034863c10f3d8669d.zip llvm-5fb8d70e5f1c5d26bfa6ca9034863c10f3d8669d.tar.gz llvm-5fb8d70e5f1c5d26bfa6ca9034863c10f3d8669d.tar.bz2 | |
ARM: Handle vldrh and vstrh in stack access hooks (#120527)
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index e6b37dd..e3e2e83 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -1330,6 +1330,7 @@ Register ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI, case ARM::tSTRspi: case ARM::VSTRD: case ARM::VSTRS: + case ARM::VSTRH: case ARM::VSTR_P0_off: case ARM::VSTR_FPSCR_NZCVQC_off: case ARM::MVE_VSTRWU32: @@ -1588,6 +1589,7 @@ Register ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, case ARM::tLDRspi: case ARM::VLDRD: case ARM::VLDRS: + case ARM::VLDRH: case ARM::VLDR_P0_off: case ARM::VLDR_FPSCR_NZCVQC_off: case ARM::MVE_VLDRWU32: |