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| author | Matthias Braun <matze@braunis.de> | 2018-11-02 18:22:15 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2018-11-02 18:22:15 +0000 |
| commit | 5f7cb79e94e6ad4f34efe1f074956b7aaa05eaef (patch) | |
| tree | 7a73c5805808a21713ef1450da096f59b9617e43 | |
| parent | 45a148de854db888b27320b1cbc4d541f304a715 (diff) | |
| download | llvm-5f7cb79e94e6ad4f34efe1f074956b7aaa05eaef.zip llvm-5f7cb79e94e6ad4f34efe1f074956b7aaa05eaef.tar.gz llvm-5f7cb79e94e6ad4f34efe1f074956b7aaa05eaef.tar.bz2 | |
ARMExpandPseudoInsts: Fix CMP_SWAP expansion adding a kill flag to a def
llvm-svn: 346026
| -rw-r--r-- | llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 9 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/cmpxchg.mir | 24 |
2 files changed, 29 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp index b35a16b..eecd0a1 100644 --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -1030,10 +1030,10 @@ static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg, if (IsThumb) { unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); - MIB.addReg(RegLo, Flags | getKillRegState(Reg.isDead())); - MIB.addReg(RegHi, Flags | getKillRegState(Reg.isDead())); + MIB.addReg(RegLo, Flags); + MIB.addReg(RegHi, Flags); } else - MIB.addReg(Reg.getReg(), Flags | getKillRegState(Reg.isDead())); + MIB.addReg(Reg.getReg(), Flags); } /// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop. @@ -1103,7 +1103,8 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB, // bne .Lloadcmp unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD; MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg); - addExclusiveRegPair(MIB, New, 0, IsThumb, TRI); + unsigned Flags = getKillRegState(New.isDead()); + addExclusiveRegPair(MIB, New, Flags, IsThumb, TRI); MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; diff --git a/llvm/test/CodeGen/ARM/cmpxchg.mir b/llvm/test/CodeGen/ARM/cmpxchg.mir new file mode 100644 index 0000000..6ae7e63 --- /dev/null +++ b/llvm/test/CodeGen/ARM/cmpxchg.mir @@ -0,0 +1,24 @@ +# RUN: llc -o - %s -mtriple=armv7-unknown-linux-gnu -verify-machineinstrs -run-pass=arm-pseudo | FileCheck %s +--- +# CHECK-LABEL: name: func +name: func +tracksRegLiveness: true +body: | + bb.0: + liveins: $r0_r1, $r4_r5, $r3, $lr + dead early-clobber renamable $r0_r1, dead early-clobber renamable $r2 = CMP_SWAP_64 killed renamable $r3, killed renamable $r4_r5, renamable $r4_r5 :: (volatile load store monotonic monotonic 8) + ; CHECK: bb.0: + ; CHECK: liveins: $r0_r1, $r4_r5, $r3, $lr + ; CHECK: bb.1: + ; CHEKC: liveins: $r4_r5, $r3 + ; CHECK: $r0_r1 = LDREXD $r3, 14, $noreg + ; CHECK: CMPrr killed $r0, $r4, 14, $noreg, implicit-def $cpsr + ; CHECK: CMPrr killed $r1, $r5, 0, killed $cpsr, implicit-def $cpsr + ; CHECK: Bcc %bb.3, 1, killed $cpsr + ; CHECK: bb.2: + ; CHECK: liveins: $r4_r5, $r3 + ; CHECK: early-clobber $r2 = STREXD $r4_r5, $r3, 14, $noreg + ; CHECK: CMPri killed $r2, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: Bcc %bb.1, 1, killed $cpsr + ; CHECK: bb.3: +... |