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| author | Alexey Bataev <a.bataev@outlook.com> | 2025-04-15 07:18:47 -0700 |
|---|---|---|
| committer | Alexey Bataev <a.bataev@outlook.com> | 2025-04-15 07:24:17 -0700 |
| commit | 57025b42c43b2f14f7e58692bc19cd53d1b8a45e (patch) | |
| tree | 081075b3c5e30ecab1187d71c3c655eb524239eb | |
| parent | 552902455c7a3958930d4607ac8b85fd39d7c8a3 (diff) | |
| download | llvm-57025b42c43b2f14f7e58692bc19cd53d1b8a45e.zip llvm-57025b42c43b2f14f7e58692bc19cd53d1b8a45e.tar.gz llvm-57025b42c43b2f14f7e58692bc19cd53d1b8a45e.tar.bz2 | |
[SLP]Mark smin reduction as signed compare
Reduction signed min must be marked as signed compare, fixing the
analysis for the cases, where the incoming arguments are unsigned.
Fixes #133943
| -rw-r--r-- | llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/Transforms/SLPVectorizer/RISCV/smin-reduction-unsigned-missing-sign.ll | 5 |
2 files changed, 7 insertions, 2 deletions
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 50c4039..f7c37d8 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -20170,6 +20170,10 @@ void BoUpSLP::computeMinimumValueSizes() { IsTruncRoot = true; } bool IsSignedCmp = false; + if (UserIgnoreList && all_of(*UserIgnoreList, [](Value *V) { + return match(V, m_SMin(m_Value(), m_Value())); + })) + IsSignedCmp = true; while (NodeIdx < VectorizableTree.size()) { ArrayRef<Value *> TreeRoot = VectorizableTree[NodeIdx]->Scalars; unsigned Limit = 2; diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/smin-reduction-unsigned-missing-sign.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/smin-reduction-unsigned-missing-sign.ll index 67f5ccc..cf7127e 100644 --- a/llvm/test/Transforms/SLPVectorizer/RISCV/smin-reduction-unsigned-missing-sign.ll +++ b/llvm/test/Transforms/SLPVectorizer/RISCV/smin-reduction-unsigned-missing-sign.ll @@ -7,8 +7,9 @@ define i32 @test(i8 %0) { ; CHECK-NEXT: [[ENTRY:.*:]] ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> <i8 poison, i8 0, i8 0, i8 0>, i8 [[TMP0]], i32 0 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i8> [[TMP1]], zeroinitializer -; CHECK-NEXT: [[TMP3:%.*]] = call i1 @llvm.vector.reduce.smin.v4i1(<4 x i1> [[TMP2]]) -; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i32 +; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i1> [[TMP2]] to <4 x i8> +; CHECK-NEXT: [[TMP5:%.*]] = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> [[TMP3]]) +; CHECK-NEXT: [[TMP4:%.*]] = zext i8 [[TMP5]] to i32 ; CHECK-NEXT: ret i32 [[TMP4]] ; entry: |