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| author | Brox Chen <guochen2@amd.com> | 2025-03-20 14:46:29 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-20 14:46:29 -0400 |
| commit | 541d6c3189cc04b5d6236972093ea3a4892a0ba8 (patch) | |
| tree | e48be343cf04af6e4d90e8c2cbd7e438e434d0b3 | |
| parent | 468452b0814a3ad04700455af2d225e25a6aecaf (diff) | |
| download | llvm-541d6c3189cc04b5d6236972093ea3a4892a0ba8.zip llvm-541d6c3189cc04b5d6236972093ea3a4892a0ba8.tar.gz llvm-541d6c3189cc04b5d6236972093ea3a4892a0ba8.tar.bz2 | |
[AMDGPU][True16][CodeGen] update VGPRimm for t16 (#131021)
added a `bitcast_fpimm_to_i16` and update the VGPRImm pattern for t16
flow.
This change is following the pattern from the 32bit case
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.td | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index 403c657..23a7f50 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -846,6 +846,11 @@ def cond_as_i32imm: SDNodeXForm<cond, [{ }]>; // Copied from the AArch64 backend: +def bitcast_fpimm_to_i16 : SDNodeXForm<fpimm, [{ +return CurDAG->getTargetConstant( + N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i16); +}]>; + def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{ return CurDAG->getTargetConstant( N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32); diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 0196a5f..4b29c6a 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -2308,7 +2308,7 @@ let True16Predicate = UseRealTrue16Insts in { foreach vt = [f16, bf16] in { def : GCNPat < (VGPRImm<(vt fpimm)>:$imm), - (V_MOV_B16_t16_e64 0, $imm, 0) + (V_MOV_B16_t16_e64 0, (vt (bitcast_fpimm_to_i16 $imm)), 0) >; } } |