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| author | Venkata Ramanaiah Nalamothu <quic_vnalamot@quicinc.com> | 2025-07-31 21:31:23 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-31 21:31:23 +0530 |
| commit | 523b4b0312ccd76d3a94e9b43779b2f6b932c43d (patch) | |
| tree | acc81a03ba61ca336bf799e5712811eafc058281 | |
| parent | b92979aae7c78021df00744d1b1c67056dae49e6 (diff) | |
| download | llvm-523b4b0312ccd76d3a94e9b43779b2f6b932c43d.zip llvm-523b4b0312ccd76d3a94e9b43779b2f6b932c43d.tar.gz llvm-523b4b0312ccd76d3a94e9b43779b2f6b932c43d.tar.bz2 | |
[Docs] Fix typo in shadow call stack option name (#151474)
Fix typo in shadow call stack option name mentioned in
'ShadowCallStack.rst'.
| -rw-r--r-- | clang/docs/ShadowCallStack.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/clang/docs/ShadowCallStack.rst b/clang/docs/ShadowCallStack.rst index fc8bea8..9b104cc 100644 --- a/clang/docs/ShadowCallStack.rst +++ b/clang/docs/ShadowCallStack.rst @@ -61,7 +61,7 @@ The instrumentation makes use of the platform register ``x18`` on AArch64, ``x3`` (``gp``) on RISC-V with software shadow stack and ``ssp`` on RISC-V with hardware shadow stack, which needs `Zicfiss`_ and ``-fcf-protection=return``. Users can choose between the software and hardware based shadow stack -implementation on RISC-V backend by passing ``-fsanitize=shadowcallstack`` +implementation on RISC-V backend by passing ``-fsanitize=shadow-call-stack`` or ``Zicfiss`` with ``-fcf-protection=return``. For simplicity we will refer to this as the ``SCSReg``. On some platforms, ``SCSReg`` is reserved, and on others, it is designated as a scratch register. |