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| author | Jim Grosbach <grosbach@apple.com> | 2011-07-13 22:59:38 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-13 22:59:38 +0000 |
| commit | 507ba774652e34e8c7aba768ca46d449b0b9ac41 (patch) | |
| tree | 8d1d8186fac8c24e9dca6ea933528c1cd0de442e | |
| parent | 48d2464c3fd8bdf6093d7ad3e4791ccab5235f6b (diff) | |
| download | llvm-507ba774652e34e8c7aba768ca46d449b0b9ac41.zip llvm-507ba774652e34e8c7aba768ca46d449b0b9ac41.tar.gz llvm-507ba774652e34e8c7aba768ca46d449b0b9ac41.tar.bz2 | |
ARM Assembler support for DBG instruction.
Add range checking and testing for parsing and encoding of DBG instruction.
llvm-svn: 135102
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 3 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/basic-arm-instructions.s | 10 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/diagnostics.s | 9 |
4 files changed, 22 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 050fd98..437f964 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -1283,9 +1283,8 @@ def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary, let Inst{8-0} = 0; } -def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", - [/* For disassembly only; pattern left blank */]>, - Requires<[IsARM, HasV7]> { +def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", + []>, Requires<[IsARM, HasV7]> { bits<4> opt; let Inst{27-4} = 0b001100100000111100001111; let Inst{3-0} = opt; diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 68fc69d..eeee041 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -3157,8 +3157,7 @@ def t2WFE : T2I_hint<0b00000010, "wfe", ".w">; def t2WFI : T2I_hint<0b00000011, "wfi", ".w">; def t2SEV : T2I_hint<0b00000100, "sev", ".w">; -def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt", - [/* For disassembly only; pattern left blank */]> { +def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> { let Inst{31-20} = 0xf3a; let Inst{15-14} = 0b10; let Inst{12} = 0; diff --git a/llvm/test/MC/ARM/basic-arm-instructions.s b/llvm/test/MC/ARM/basic-arm-instructions.s index 3708ec5..f2d5f7f 100644 --- a/llvm/test/MC/ARM/basic-arm-instructions.s +++ b/llvm/test/MC/ARM/basic-arm-instructions.s @@ -448,3 +448,13 @@ _func: @ CHECK: cmp r7, r8, ror r2 @ encoding: [0x78,0x02,0x57,0xe1] @ CHECK: cmp r1, r6, rrx @ encoding: [0x66,0x00,0x51,0xe1] +@------------------------------------------------------------------------------ +@ DBG +@------------------------------------------------------------------------------ + dbg #0 + dbg #5 + dbg #15 + +@ CHECK: dbg #0 @ encoding: [0xf0,0xf0,0x20,0xe3] +@ CHECK: dbg #5 @ encoding: [0xf5,0xf0,0x20,0xe3] +@ CHECK: dbg #15 @ encoding: [0xff,0xf0,0x20,0xe3] diff --git a/llvm/test/MC/ARM/diagnostics.s b/llvm/test/MC/ARM/diagnostics.s index 4069fea50..a173cdb 100644 --- a/llvm/test/MC/ARM/diagnostics.s +++ b/llvm/test/MC/ARM/diagnostics.s @@ -59,3 +59,12 @@ @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction + + @ Out of range immediates for DBG + dbg #-1 + dbg #16 + +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ Double-check that we're synced up with the right diagnostics. +@ CHECK-ERRORS: dbg #16 |