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author | Madhur Amilkanthwar <madhura@nvidia.com> | 2025-07-30 10:52:33 +0530 |
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committer | GitHub <noreply@github.com> | 2025-07-30 10:52:33 +0530 |
commit | 4ee6943eeb1de19e182b56fde34d134d43aceb67 (patch) | |
tree | caab74beb4e335d004f76d18e814d4a7b8484ee8 | |
parent | 74763608ef0da6bdcf6032f0457d1e7a156bad6a (diff) | |
download | llvm-4ee6943eeb1de19e182b56fde34d134d43aceb67.zip llvm-4ee6943eeb1de19e182b56fde34d134d43aceb67.tar.gz llvm-4ee6943eeb1de19e182b56fde34d134d43aceb67.tar.bz2 |
[GVN][Tests] Add MSSA coverage to some PRE tests 3/N (#150603)
Previous patch in this series
https://github.com/llvm/llvm-project/pull/137814
-rw-r--r-- | llvm/test/Transforms/GVN/PRE/load-metadata.ll | 47 | ||||
-rw-r--r-- | llvm/test/Transforms/GVN/PRE/load-pre-across-backedge.ll | 6 | ||||
-rw-r--r-- | llvm/test/Transforms/GVN/PRE/load-pre-nonlocal.ll | 6 | ||||
-rw-r--r-- | llvm/test/Transforms/GVN/PRE/lpre-call-wrap.ll | 80 | ||||
-rw-r--r-- | llvm/test/Transforms/GVN/PRE/rle-addrspace-cast.ll | 24 | ||||
-rw-r--r-- | llvm/test/Transforms/GVN/PRE/rle-semidominated.ll | 55 |
6 files changed, 162 insertions, 56 deletions
diff --git a/llvm/test/Transforms/GVN/PRE/load-metadata.ll b/llvm/test/Transforms/GVN/PRE/load-metadata.ll index 415812b..1128b1b 100644 --- a/llvm/test/Transforms/GVN/PRE/load-metadata.ll +++ b/llvm/test/Transforms/GVN/PRE/load-metadata.ll @@ -1,14 +1,40 @@ -; RUN: opt -S -passes=gvn < %s | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt -S -passes=gvn < %s | FileCheck %s --check-prefixes=CHECK,MDEP +; RUN: opt -S -passes='gvn<memoryssa>' < %s | FileCheck %s --check-prefixes=CHECK,MSSA define i32 @test1(ptr %p, i1 %C) { -; CHECK-LABEL: @test1( +; MDEP-LABEL: define i32 @test1( +; MDEP-SAME: ptr [[P:%.*]], i1 [[C:%.*]]) { +; MDEP-NEXT: [[BLOCK1:.*:]] +; MDEP-NEXT: br i1 [[C]], label %[[BLOCK2:.*]], label %[[BLOCK3:.*]] +; MDEP: [[BLOCK2]]: +; MDEP-NEXT: [[PRE_PRE:%.*]] = load i32, ptr [[P]], align 4, !range [[RNG0:![0-9]+]], !invariant.group [[META1:![0-9]+]] +; MDEP-NEXT: br label %[[BLOCK4:.*]] +; MDEP: [[BLOCK3]]: +; MDEP-NEXT: store i32 0, ptr [[P]], align 4 +; MDEP-NEXT: br label %[[BLOCK4]] +; MDEP: [[BLOCK4]]: +; MDEP-NEXT: [[PRE:%.*]] = phi i32 [ 0, %[[BLOCK3]] ], [ [[PRE_PRE]], %[[BLOCK2]] ] +; MDEP-NEXT: ret i32 [[PRE]] +; +; MSSA-LABEL: define i32 @test1( +; MSSA-SAME: ptr [[P:%.*]], i1 [[C:%.*]]) { +; MSSA-NEXT: [[BLOCK1:.*:]] +; MSSA-NEXT: br i1 [[C]], label %[[BLOCK2:.*]], label %[[BLOCK3:.*]] +; MSSA: [[BLOCK2]]: +; MSSA-NEXT: br label %[[BLOCK4:.*]] +; MSSA: [[BLOCK3]]: +; MSSA-NEXT: store i32 0, ptr [[P]], align 4 +; MSSA-NEXT: br label %[[BLOCK4]] +; MSSA: [[BLOCK4]]: +; MSSA-NEXT: [[PRE:%.*]] = load i32, ptr [[P]], align 4, !range [[RNG0:![0-9]+]], !invariant.group [[META1:![0-9]+]] +; MSSA-NEXT: ret i32 [[PRE]] +; block1: - br i1 %C, label %block2, label %block3 + br i1 %C, label %block2, label %block3 block2: - br label %block4 -; CHECK: block2: -; CHECK-NEXT: load i32, ptr %p, align 4, !range !0, !invariant.group !1 + br label %block4 block3: store i32 0, ptr %p @@ -22,3 +48,12 @@ block4: !0 = !{i32 40, i32 100} !1 = !{!"magic ptr"} +;. +; MDEP: [[RNG0]] = !{i32 40, i32 100} +; MDEP: [[META1]] = !{!"magic ptr"} +;. +; MSSA: [[RNG0]] = !{i32 40, i32 100} +; MSSA: [[META1]] = !{!"magic ptr"} +;. +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK: {{.*}} diff --git a/llvm/test/Transforms/GVN/PRE/load-pre-across-backedge.ll b/llvm/test/Transforms/GVN/PRE/load-pre-across-backedge.ll index a3eae62..b677272 100644 --- a/llvm/test/Transforms/GVN/PRE/load-pre-across-backedge.ll +++ b/llvm/test/Transforms/GVN/PRE/load-pre-across-backedge.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -passes=gvn -S < %s | FileCheck %s +; RUN: opt -passes=gvn -S < %s | FileCheck %s --check-prefixes=CHECK,MDEP +; RUN: opt -passes='gvn<memoryssa>' -S < %s | FileCheck %s --check-prefixes=CHECK,MSSA ; Check that PRE-LOAD across backedge does not ; result in invalid dominator tree. @@ -43,3 +44,6 @@ bb3: call void @use(i32 %v) br label %bb2 } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; MDEP: {{.*}} +; MSSA: {{.*}} diff --git a/llvm/test/Transforms/GVN/PRE/load-pre-nonlocal.ll b/llvm/test/Transforms/GVN/PRE/load-pre-nonlocal.ll index b778d98..9dba73a 100644 --- a/llvm/test/Transforms/GVN/PRE/load-pre-nonlocal.ll +++ b/llvm/test/Transforms/GVN/PRE/load-pre-nonlocal.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -o - -passes=gvn %s | FileCheck %s +; RUN: opt -S -o - -passes=gvn %s | FileCheck %s --check-prefixes=CHECK,MDEP +; RUN: opt -S -o - -passes='gvn<memoryssa>' %s | FileCheck %s --check-prefixes=CHECK,MSSA target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" @@ -143,3 +144,6 @@ if.end: file: !12, isOptimized: true, flags: "-O2", splitDebugFilename: "abc.debug", emissionKind: 2) +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; MDEP: {{.*}} +; MSSA: {{.*}} diff --git a/llvm/test/Transforms/GVN/PRE/lpre-call-wrap.ll b/llvm/test/Transforms/GVN/PRE/lpre-call-wrap.ll index 06a7f11..9b4eb60 100644 --- a/llvm/test/Transforms/GVN/PRE/lpre-call-wrap.ll +++ b/llvm/test/Transforms/GVN/PRE/lpre-call-wrap.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -passes=gvn -enable-load-pre < %s | FileCheck %s +; RUN: opt -S -passes=gvn -enable-load-pre < %s | FileCheck %s --check-prefixes=CHECK,MDEP +; RUN: opt -S -passes='gvn<memoryssa>' -enable-load-pre < %s | FileCheck %s --check-prefixes=CHECK,MSSA ; ; Make sure the load in bb3.backedge is removed and moved into bb1 after the ; call. This makes the non-call case faster. @@ -18,31 +19,56 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3 %struct.A = type { i32, i32 } define void @_Z12testfunctionR1A(ptr %iter) { -; CHECK-LABEL: @_Z12testfunctionR1A( -; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ITER:%.*]], align 4 -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 0 -; CHECK-NEXT: br i1 [[TMP1]], label [[RETURN:%.*]], label [[BB_NPH:%.*]] -; CHECK: bb.nph: -; CHECK-NEXT: [[TMP2:%.*]] = getelementptr [[STRUCT_A:%.*]], ptr [[ITER]], i32 0, i32 1 -; CHECK-NEXT: br label [[BB:%.*]] -; CHECK: bb: -; CHECK-NEXT: [[DOTRLE:%.*]] = phi i32 [ [[TMP0]], [[BB_NPH]] ], [ [[TMP6:%.*]], [[BB3_BACKEDGE:%.*]] ] -; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[DOTRLE]], 1 -; CHECK-NEXT: store i32 [[TMP3]], ptr [[ITER]], align 4 -; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4 -; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP3]], [[TMP4]] -; CHECK-NEXT: br i1 [[TMP5]], label [[BB1:%.*]], label [[BB3_BACKEDGE]] -; CHECK: bb1: -; CHECK-NEXT: tail call void @_Z1gv() -; CHECK-NEXT: [[DOTPRE:%.*]] = load i32, ptr [[ITER]], align 4 -; CHECK-NEXT: br label [[BB3_BACKEDGE]] -; CHECK: bb3.backedge: -; CHECK-NEXT: [[TMP6]] = phi i32 [ [[DOTPRE]], [[BB1]] ], [ [[TMP3]], [[BB]] ] -; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0 -; CHECK-NEXT: br i1 [[TMP7]], label [[RETURN]], label [[BB]] -; CHECK: return: -; CHECK-NEXT: ret void +; MDEP-LABEL: @_Z12testfunctionR1A( +; MDEP-NEXT: entry: +; MDEP-NEXT: [[TMP0:%.*]] = load i32, ptr [[ITER:%.*]], align 4 +; MDEP-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 0 +; MDEP-NEXT: br i1 [[TMP1]], label [[RETURN:%.*]], label [[BB_NPH:%.*]] +; MDEP: bb.nph: +; MDEP-NEXT: [[TMP2:%.*]] = getelementptr [[STRUCT_A:%.*]], ptr [[ITER]], i32 0, i32 1 +; MDEP-NEXT: br label [[BB:%.*]] +; MDEP: bb: +; MDEP-NEXT: [[DOTRLE:%.*]] = phi i32 [ [[TMP0]], [[BB_NPH]] ], [ [[TMP6:%.*]], [[BB3_BACKEDGE:%.*]] ] +; MDEP-NEXT: [[TMP3:%.*]] = add i32 [[DOTRLE]], 1 +; MDEP-NEXT: store i32 [[TMP3]], ptr [[ITER]], align 4 +; MDEP-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4 +; MDEP-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP3]], [[TMP4]] +; MDEP-NEXT: br i1 [[TMP5]], label [[BB1:%.*]], label [[BB3_BACKEDGE]] +; MDEP: bb1: +; MDEP-NEXT: tail call void @_Z1gv() +; MDEP-NEXT: [[DOTPRE:%.*]] = load i32, ptr [[ITER]], align 4 +; MDEP-NEXT: br label [[BB3_BACKEDGE]] +; MDEP: bb3.backedge: +; MDEP-NEXT: [[TMP6]] = phi i32 [ [[DOTPRE]], [[BB1]] ], [ [[TMP3]], [[BB]] ] +; MDEP-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0 +; MDEP-NEXT: br i1 [[TMP7]], label [[RETURN]], label [[BB]] +; MDEP: return: +; MDEP-NEXT: ret void +; +; MSSA-LABEL: @_Z12testfunctionR1A( +; MSSA-NEXT: entry: +; MSSA-NEXT: [[TMP0:%.*]] = load i32, ptr [[ITER:%.*]], align 4 +; MSSA-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 0 +; MSSA-NEXT: br i1 [[TMP1]], label [[RETURN:%.*]], label [[BB_NPH:%.*]] +; MSSA: bb.nph: +; MSSA-NEXT: [[TMP2:%.*]] = getelementptr [[STRUCT_A:%.*]], ptr [[ITER]], i32 0, i32 1 +; MSSA-NEXT: br label [[BB:%.*]] +; MSSA: bb: +; MSSA-NEXT: [[DOTRLE:%.*]] = phi i32 [ [[TMP0]], [[BB_NPH]] ], [ [[TMP6:%.*]], [[BB3_BACKEDGE:%.*]] ] +; MSSA-NEXT: [[TMP3:%.*]] = add i32 [[DOTRLE]], 1 +; MSSA-NEXT: store i32 [[TMP3]], ptr [[ITER]], align 4 +; MSSA-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4 +; MSSA-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP3]], [[TMP4]] +; MSSA-NEXT: br i1 [[TMP5]], label [[BB1:%.*]], label [[BB3_BACKEDGE]] +; MSSA: bb1: +; MSSA-NEXT: tail call void @_Z1gv() +; MSSA-NEXT: br label [[BB3_BACKEDGE]] +; MSSA: bb3.backedge: +; MSSA-NEXT: [[TMP6]] = load i32, ptr [[ITER]], align 4 +; MSSA-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0 +; MSSA-NEXT: br i1 [[TMP7]], label [[RETURN]], label [[BB]] +; MSSA: return: +; MSSA-NEXT: ret void ; entry: %0 = getelementptr %struct.A, ptr %iter, i32 0, i32 0 ; <ptr> [#uses=3] @@ -76,3 +102,5 @@ return: ; preds = %bb3.backedge, %entry } declare void @_Z1gv() +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK: {{.*}} diff --git a/llvm/test/Transforms/GVN/PRE/rle-addrspace-cast.ll b/llvm/test/Transforms/GVN/PRE/rle-addrspace-cast.ll index 7f67b2b..6c79b02 100644 --- a/llvm/test/Transforms/GVN/PRE/rle-addrspace-cast.ll +++ b/llvm/test/Transforms/GVN/PRE/rle-addrspace-cast.ll @@ -1,6 +1,23 @@ -; RUN: opt < %s -data-layout="e-p:32:32:32-p1:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-n8:16:32" -passes=gvn,dce -S | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt < %s -data-layout="e-p:32:32:32-p1:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-n8:16:32" -passes=gvn,dce -S | FileCheck %s --check-prefixes=CHECK,MDEP +; RUN: opt < %s -data-layout="e-p:32:32:32-p1:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-n8:16:32" -passes='gvn<memoryssa>',dce -S | FileCheck %s --check-prefixes=CHECK,MSSA define i8 @coerce_offset0_addrspacecast(i32 %V, ptr %P) { +; MDEP-LABEL: define i8 @coerce_offset0_addrspacecast( +; MDEP-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) { +; MDEP-NEXT: store i32 [[V]], ptr [[P]], align 4 +; MDEP-NEXT: [[TMP1:%.*]] = lshr i32 [[V]], 16 +; MDEP-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8 +; MDEP-NEXT: ret i8 [[TMP2]] +; +; MSSA-LABEL: define i8 @coerce_offset0_addrspacecast( +; MSSA-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) { +; MSSA-NEXT: store i32 [[V]], ptr [[P]], align 4 +; MSSA-NEXT: [[P2:%.*]] = addrspacecast ptr [[P]] to ptr addrspace(1) +; MSSA-NEXT: [[P3:%.*]] = getelementptr i8, ptr addrspace(1) [[P2]], i32 2 +; MSSA-NEXT: [[A:%.*]] = load i8, ptr addrspace(1) [[P3]], align 1 +; MSSA-NEXT: ret i8 [[A]] +; store i32 %V, ptr %P %P2 = addrspacecast ptr %P to ptr addrspace(1) @@ -8,7 +25,6 @@ define i8 @coerce_offset0_addrspacecast(i32 %V, ptr %P) { %A = load i8, ptr addrspace(1) %P3 ret i8 %A -; CHECK-LABEL: @coerce_offset0_addrspacecast( -; CHECK-NOT: load -; CHECK: ret i8 } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK: {{.*}} diff --git a/llvm/test/Transforms/GVN/PRE/rle-semidominated.ll b/llvm/test/Transforms/GVN/PRE/rle-semidominated.ll index e927f37..4eb090e 100644 --- a/llvm/test/Transforms/GVN/PRE/rle-semidominated.ll +++ b/llvm/test/Transforms/GVN/PRE/rle-semidominated.ll @@ -1,13 +1,45 @@ -; RUN: opt < %s -passes=gvn -S | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt < %s -passes=gvn -S | FileCheck %s --check-prefixes=CHECK,MDEP +; RUN: opt < %s -passes='gvn<memoryssa>' -S | FileCheck %s --check-prefixes=CHECK,MSSA define i32 @main(ptr %p, i32 %x, i32 %y) { +; MDEP-LABEL: define i32 @main( +; MDEP-SAME: ptr [[P:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]) { +; MDEP-NEXT: [[BLOCK1:.*:]] +; MDEP-NEXT: [[CMP:%.*]] = icmp eq i32 [[X]], [[Y]] +; MDEP-NEXT: br i1 [[CMP]], label %[[BLOCK2:.*]], label %[[BLOCK3:.*]] +; MDEP: [[BLOCK2]]: +; MDEP-NEXT: [[DEAD_PRE:%.*]] = load i32, ptr [[P]], align 4 +; MDEP-NEXT: br label %[[BLOCK4:.*]] +; MDEP: [[BLOCK3]]: +; MDEP-NEXT: store i32 0, ptr [[P]], align 4 +; MDEP-NEXT: br label %[[BLOCK4]] +; MDEP: [[BLOCK4]]: +; MDEP-NEXT: [[DEAD:%.*]] = phi i32 [ 0, %[[BLOCK3]] ], [ [[DEAD_PRE]], %[[BLOCK2]] ] +; MDEP-NEXT: ret i32 [[DEAD]] +; +; MSSA-LABEL: define i32 @main( +; MSSA-SAME: ptr [[P:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]) { +; MSSA-NEXT: [[BLOCK1:.*:]] +; MSSA-NEXT: [[Z:%.*]] = load i32, ptr [[P]], align 4 +; MSSA-NEXT: [[CMP:%.*]] = icmp eq i32 [[X]], [[Y]] +; MSSA-NEXT: br i1 [[CMP]], label %[[BLOCK2:.*]], label %[[BLOCK3:.*]] +; MSSA: [[BLOCK2]]: +; MSSA-NEXT: br label %[[BLOCK4:.*]] +; MSSA: [[BLOCK3]]: +; MSSA-NEXT: store i32 0, ptr [[P]], align 4 +; MSSA-NEXT: br label %[[BLOCK4]] +; MSSA: [[BLOCK4]]: +; MSSA-NEXT: [[DEAD:%.*]] = load i32, ptr [[P]], align 4 +; MSSA-NEXT: ret i32 [[DEAD]] +; block1: %z = load i32, ptr %p %cmp = icmp eq i32 %x, %y - br i1 %cmp, label %block2, label %block3 + br i1 %cmp, label %block2, label %block3 block2: - br label %block4 + br label %block4 block3: %b = bitcast i32 0 to i32 @@ -19,18 +51,5 @@ block4: ret i32 %DEAD } -; CHECK: define i32 @main(ptr %p, i32 %x, i32 %y) { -; CHECK-NEXT: block1: -; CHECK-NOT: %z = load i32, ptr %p -; CHECK-NEXT: %cmp = icmp eq i32 %x, %y -; CHECK-NEXT: br i1 %cmp, label %block2, label %block3 -; CHECK: block2: -; CHECK-NEXT: %DEAD.pre = load i32, ptr %p -; CHECK-NEXT: br label %block4 -; CHECK: block3: -; CHECK-NEXT: store i32 0, ptr %p -; CHECK-NEXT: br label %block4 -; CHECK: block4: -; CHECK-NEXT: %DEAD = phi i32 [ 0, %block3 ], [ %DEAD.pre, %block2 ] -; CHECK-NEXT: ret i32 %DEAD -; CHECK-NEXT: } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK: {{.*}} |