diff options
| author | Alexey Bataev <a.bataev@outlook.com> | 2023-03-01 06:34:52 -0800 |
|---|---|---|
| committer | Alexey Bataev <a.bataev@outlook.com> | 2023-03-01 06:35:56 -0800 |
| commit | 4e4ad3ab0ec9c34bda843067976af24ea07a305d (patch) | |
| tree | 23dc94fe0934c24175e67ae4ba2ab3f938832a27 | |
| parent | ddccc5ba4479a36dd4821f0948e118438fbf2e56 (diff) | |
| download | llvm-4e4ad3ab0ec9c34bda843067976af24ea07a305d.zip llvm-4e4ad3ab0ec9c34bda843067976af24ea07a305d.tar.gz llvm-4e4ad3ab0ec9c34bda843067976af24ea07a305d.tar.bz2 | |
[SLP][NFC]Update the test to simplify and avoid dead instruction
removal, NFC.
| -rw-r--r-- | llvm/test/Transforms/SLPVectorizer/X86/PR35865.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/PR35865.ll b/llvm/test/Transforms/SLPVectorizer/X86/PR35865.ll index f961d60..244faa4 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/PR35865.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/PR35865.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -passes=slp-vectorizer < %s -S -o - -mtriple=x86_64-apple-macosx10.10.0 -mcpu=core2 | FileCheck %s -define void @_Z10fooConvertPDv4_xS0_S0_PKS_() { -; CHECK-LABEL: @_Z10fooConvertPDv4_xS0_S0_PKS_( +define void @test(<16 x half> %v) { +; CHECK-LABEL: @test( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = extractelement <16 x half> undef, i32 4 -; CHECK-NEXT: [[TMP1:%.*]] = extractelement <16 x half> undef, i32 5 +; CHECK-NEXT: [[TMP0:%.*]] = extractelement <16 x half> [[V:%.*]], i32 4 +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <16 x half> [[V]], i32 5 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x half> poison, half [[TMP0]], i32 0 ; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x half> [[TMP2]], half [[TMP1]], i32 1 ; CHECK-NEXT: [[TMP4:%.*]] = fpext <2 x half> [[TMP3]] to <2 x float> @@ -15,11 +15,11 @@ define void @_Z10fooConvertPDv4_xS0_S0_PKS_() { ; CHECK-NEXT: ret void ; entry: - %0 = extractelement <16 x half> undef, i32 4 + %0 = extractelement <16 x half> %v, i32 4 %conv.i.4.i = fpext half %0 to float %1 = bitcast float %conv.i.4.i to i32 %vecins.i.4.i = insertelement <8 x i32> undef, i32 %1, i32 4 - %2 = extractelement <16 x half> undef, i32 5 + %2 = extractelement <16 x half> %v, i32 5 %conv.i.5.i = fpext half %2 to float %3 = bitcast float %conv.i.5.i to i32 %vecins.i.5.i = insertelement <8 x i32> %vecins.i.4.i, i32 %3, i32 5 |