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authorRamkumar Ramachandra <ram.ramachandra@arm.com>2024-04-19 10:01:51 +0100
committerGitHub <noreply@github.com>2024-04-19 10:01:51 +0100
commit494c637816e4787752ae3bf29be618ffdc92f4cd (patch)
tree3295dcb0a007ea5c21d8a48a9c940e7560aac2c9
parent7c7704c946ab6078c42b24a57eb537944861cba1 (diff)
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MachineInstrBundle: modernize a couple of loops (NFC) (#89229)
-rw-r--r--llvm/lib/CodeGen/MachineInstrBundle.cpp7
1 files changed, 2 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/MachineInstrBundle.cpp b/llvm/lib/CodeGen/MachineInstrBundle.cpp
index 6eeed8b..dafa8e2 100644
--- a/llvm/lib/CodeGen/MachineInstrBundle.cpp
+++ b/llvm/lib/CodeGen/MachineInstrBundle.cpp
@@ -312,8 +312,7 @@ llvm::AnalyzeVirtRegLanesInBundle(const MachineInstr &MI, Register Reg,
LaneBitmask UseMask, DefMask;
- for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
- const MachineOperand &MO = *O;
+ for (const MachineOperand &MO : const_mi_bundle_ops(MI)) {
if (!MO.isReg() || MO.getReg() != Reg)
continue;
@@ -339,9 +338,7 @@ PhysRegInfo llvm::AnalyzePhysRegInBundle(const MachineInstr &MI, Register Reg,
PhysRegInfo PRI = {false, false, false, false, false, false, false, false};
assert(Reg.isPhysical() && "analyzePhysReg not given a physical register!");
- for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
- const MachineOperand &MO = *O;
-
+ for (const MachineOperand &MO : const_mi_bundle_ops(MI)) {
if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) {
PRI.Clobbered = true;
continue;