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| author | Zi Xuan Wu <zixuan.wu@linux.alibaba.com> | 2022-04-08 14:34:21 +0800 |
|---|---|---|
| committer | Zi Xuan Wu <zixuan.wu@linux.alibaba.com> | 2022-04-08 14:37:07 +0800 |
| commit | 3d4ca8a8c39f772dd6c022220a6eef23238a77f6 (patch) | |
| tree | 3eb9d67103966fa43215f38d856d4b1636c99a12 | |
| parent | 0c789db541c236abf47265331a2f2b0945aa7b93 (diff) | |
| download | llvm-3d4ca8a8c39f772dd6c022220a6eef23238a77f6.zip llvm-3d4ca8a8c39f772dd6c022220a6eef23238a77f6.tar.gz llvm-3d4ca8a8c39f772dd6c022220a6eef23238a77f6.tar.bz2 | |
[CSKY] Correct the alignment of FPR register
The alignment of FPR64 and sFPR64 declared in RegisterClass should be 32 bit.
| -rw-r--r-- | llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/CSKY/CSKYRegisterInfo.td | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp b/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp index f67147a..0d27187 100644 --- a/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp +++ b/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp @@ -1721,9 +1721,9 @@ unsigned CSKYAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, if (CSKYMCRegisterClasses[CSKY::FPR32RegClassID].contains(Reg)) { // As the parser couldn't differentiate an FPR64 from an FPR32, coerce the // register from FPR32 to FPR64 if necessary. - if (Kind == MCK_FPR64 || Kind == MCK_sFPR64_V) { + if (Kind == MCK_FPR64 || Kind == MCK_sFPR64) { Op.Reg.RegNum = convertFPR32ToFPR64(Reg); - if (Kind == MCK_sFPR64_V && + if (Kind == MCK_sFPR64 && (Op.Reg.RegNum < CSKY::F0_64 || Op.Reg.RegNum > CSKY::F15_64)) return Match_InvalidRegOutOfRange; if (Kind == MCK_FPR64 && diff --git a/llvm/lib/Target/CSKY/CSKYRegisterInfo.td b/llvm/lib/Target/CSKY/CSKYRegisterInfo.td index d72bf81..d12532a 100644 --- a/llvm/lib/Target/CSKY/CSKYRegisterInfo.td +++ b/llvm/lib/Target/CSKY/CSKYRegisterInfo.td @@ -193,9 +193,9 @@ def FPR32 : RegisterClass<"CSKY", [f32], 32, def sFPR32 : RegisterClass<"CSKY", [f32], 32, (add (sequence "F%u_32", 0, 15))>; -def FPR64 : RegisterClass<"CSKY", [f64], 64, +def FPR64 : RegisterClass<"CSKY", [f64], 32, (add (sequence "F%u_64", 0, 31))>; -def sFPR64 : RegisterClass<"CSKY", [f64], 64, +def sFPR64 : RegisterClass<"CSKY", [f64], 32, (add (sequence "F%u_64", 0, 15))>; def sFPR64_V : RegisterClass<"CSKY", [v2f32], 32, (add sFPR64)>; |