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| author | Sam Parker <sam.parker@arm.com> | 2020-01-10 13:08:30 +0000 |
|---|---|---|
| committer | Sam Parker <sam.parker@arm.com> | 2020-01-10 14:24:25 +0000 |
| commit | 3772ea9dd9368cfdc73595854c143bc3f16a5ade (patch) | |
| tree | 9fc551cae83473c47fe751bfe88d61df9175af33 | |
| parent | 2f2f41e12c5201b600d887d22ce5cb4afd2ff594 (diff) | |
| download | llvm-3772ea9dd9368cfdc73595854c143bc3f16a5ade.zip llvm-3772ea9dd9368cfdc73595854c143bc3f16a5ade.tar.gz llvm-3772ea9dd9368cfdc73595854c143bc3f16a5ade.tar.bz2 | |
[ARM][MVE] Tail predicate VMAX,VMAXA,VMIN,VMINA
Add the MVE min and max instructions to our tail predication
whitelist.
Differential Revision: https://reviews.llvm.org/D72502
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrMVE.td | 2 | ||||
| -rw-r--r-- | llvm/unittests/Target/ARM/MachineInstrTest.cpp | 18 |
2 files changed, 20 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td index 19dadf2..2b454b4 100644 --- a/llvm/lib/Target/ARM/ARMInstrMVE.td +++ b/llvm/lib/Target/ARM/ARMInstrMVE.td @@ -1138,6 +1138,7 @@ class MVE_VMINMAX<string iname, string suffix, bit U, bits<2> size, let Inst{8} = 0b0; let Inst{6} = 0b1; let Inst{4} = bit_4; + let validForTailPredication = 1; } multiclass MVE_VMINMAX_m<string iname, bit bit_4, MVEVectorVTInfo VTI, @@ -2298,6 +2299,7 @@ class MVE_VMINMAXA<string iname, string suffix, bits<2> size, let Inst{4} = 0b0; let Inst{3-1} = Qm{2-0}; let Inst{0} = 0b1; + let validForTailPredication = 1; } def MVE_VMAXAs8 : MVE_VMINMAXA<"vmaxa", "s8", 0b00, 0b0>; diff --git a/llvm/unittests/Target/ARM/MachineInstrTest.cpp b/llvm/unittests/Target/ARM/MachineInstrTest.cpp index 581d8be..f5b7414 100644 --- a/llvm/unittests/Target/ARM/MachineInstrTest.cpp +++ b/llvm/unittests/Target/ARM/MachineInstrTest.cpp @@ -149,6 +149,24 @@ TEST(MachineInstrValidTailPredication, IsCorrect) { case MVE_VFMA_qr_Sf32: case MVE_VFMA_qr_f16: case MVE_VFMA_qr_f32: + case MVE_VMAXAs16: + case MVE_VMAXAs32: + case MVE_VMAXAs8: + case MVE_VMAXs16: + case MVE_VMAXs32: + case MVE_VMAXs8: + case MVE_VMAXu16: + case MVE_VMAXu32: + case MVE_VMAXu8: + case MVE_VMINAs16: + case MVE_VMINAs32: + case MVE_VMINAs8: + case MVE_VMINs16: + case MVE_VMINs32: + case MVE_VMINs8: + case MVE_VMINu16: + case MVE_VMINu32: + case MVE_VMINu8: case MVE_VMLAS_qr_s16: case MVE_VMLAS_qr_s32: case MVE_VMLAS_qr_s8: |