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| author | Hal Finkel <hfinkel@anl.gov> | 2013-03-27 13:00:56 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-03-27 13:00:56 +0000 |
| commit | 35dd5c5932a47b42f3a446cd014a0332cab6b80c (patch) | |
| tree | 011d2b851f85effc0b3676caa84d9911428522ae | |
| parent | b0d0aa5cdc8608dd451a71446738d63d56711314 (diff) | |
| download | llvm-35dd5c5932a47b42f3a446cd014a0332cab6b80c.zip llvm-35dd5c5932a47b42f3a446cd014a0332cab6b80c.tar.gz llvm-35dd5c5932a47b42f3a446cd014a0332cab6b80c.tar.bz2 | |
Fix target-customized spilling in the register scavenger
This is a follow-up to r178073 (which should actually make target-customized
spilling work again).
I still don't have a regression test for this (but it would be good to have
one; Thumb 1 and Mips16 use this callback as well).
Patch by Richard Sandiford.
llvm-svn: 178137
| -rw-r--r-- | llvm/lib/CodeGen/RegisterScavenging.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp index 6b85cd9..55a66ba 100644 --- a/llvm/lib/CodeGen/RegisterScavenging.cpp +++ b/llvm/lib/CodeGen/RegisterScavenging.cpp @@ -371,7 +371,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, if (Scavenged[SI].Reg == 0) break; - if (SI < Scavenged.size()) { + if (SI == Scavenged.size()) { // We need to scavenge a register but have no spill slot, the target // must know how to do it (if not, we'll assert below). Scavenged.push_back(ScavengedInfo()); |