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| author | Michael Maitland <michaeltmaitland@gmail.com> | 2023-08-31 11:27:23 -0700 |
|---|---|---|
| committer | Michael Maitland <michaeltmaitland@gmail.com> | 2023-09-05 09:34:47 -0700 |
| commit | 3065ce1ee32b779348dcfecc9fd2b280c0ca9508 (patch) | |
| tree | d44d5d1196a2553a296dd35c22d517c606397195 | |
| parent | 6f8b17703da2fbabba974b82578530b152b79c26 (diff) | |
| download | llvm-3065ce1ee32b779348dcfecc9fd2b280c0ca9508.zip llvm-3065ce1ee32b779348dcfecc9fd2b280c0ca9508.tar.gz llvm-3065ce1ee32b779348dcfecc9fd2b280c0ca9508.tar.bz2 | |
[RISCV][llvm-mca] Fix Fix getLMUL values
These values come from RISCVInstrInfoVPseudos.td. MF8 and MF2 were
swapped by accident.
Differential Revision: https://reviews.llvm.org/D159301
| -rw-r--r-- | llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s | 55 |
2 files changed, 57 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp index 70111a2..16f9c11 100644 --- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp +++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp @@ -63,9 +63,9 @@ uint8_t RISCVLMULInstrument::getLMUL() const { .Case("M2", 0b001) .Case("M4", 0b010) .Case("M8", 0b011) - .Case("MF2", 0b101) + .Case("MF2", 0b111) .Case("MF4", 0b110) - .Case("MF8", 0b111); + .Case("MF8", 0b101); } const llvm::StringRef RISCVSEWInstrument::DESC_NAME = "RISCV-SEW"; diff --git a/llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s b/llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s new file mode 100644 index 0000000..a72e87f --- /dev/null +++ b/llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s @@ -0,0 +1,55 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s | FileCheck %s + +# TODO: This test should be replaced by an exhaustive test of legal (LMUL, SEW) +# pairs for all instructions in the Vector Integer Arithmetic chapter of the RVV +# SPEC. +vsetvli zero, zero, e32, mf2, tu, mu +vdiv.vv v12, v12, v12 +vsetvli zero, zero, e8, mf8, tu, mu +vdiv.vv v12, v12, v12 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 4 +# CHECK-NEXT: Total Cycles: 90 +# CHECK-NEXT: Total uOps: 4 + +# CHECK: Dispatch Width: 2 +# CHECK-NEXT: uOps Per Cycle: 0.04 +# CHECK-NEXT: IPC: 0.04 +# CHECK-NEXT: Block RThroughput: 86.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu +# CHECK-NEXT: 1 56 56.00 vdiv.vv v12, v12, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu +# CHECK-NEXT: 1 30 30.00 vdiv.vv v12, v12, v12 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SiFive7FDiv +# CHECK-NEXT: [1] - SiFive7IDiv +# CHECK-NEXT: [2] - SiFive7PipeA +# CHECK-NEXT: [3] - SiFive7PipeB +# CHECK-NEXT: [4] - SiFive7PipeV +# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [6] - SiFive7VL +# CHECK-NEXT: [7] - SiFive7VS + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] +# CHECK-NEXT: - - 2.00 - 86.00 86.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu +# CHECK-NEXT: - - - - 56.00 56.00 - - vdiv.vv v12, v12, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu +# CHECK-NEXT: - - - - 30.00 30.00 - - vdiv.vv v12, v12, v12 |