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authorPhilip Reames <preames@rivosinc.com>2025-03-19 13:33:49 -0700
committerPhilip Reames <listmail@philipreames.com>2025-03-19 13:36:25 -0700
commit2a53358eea7f8da9ffb92d375976b3f78ce5f212 (patch)
tree5642837667185e51312d1e1f15ab83e4a195f404
parent8e773d8a10cc996fbbe834f59ed9f7044c3539e0 (diff)
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[RISCV] Add a comment to clarify purpose of a test from 93b8ef
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll6
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
index 75eb75f..4dde731 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
@@ -120,6 +120,9 @@ entry:
ret <4 x i32> %c
}
+; This is the zipeven pattern with a poison second operand. That happens
+; to also be described as an identity shuffle, so this is testing that we
+; don't emit the zipeven instruction.
define <4 x i32> @zipeven_v4i32_single(<4 x i32> %a) {
; CHECK-LABEL: zipeven_v4i32_single:
; CHECK: # %bb.0: # %entry
@@ -129,6 +132,9 @@ entry:
ret <4 x i32> %c
}
+; This is the zipodd pattern with a poison second operand. That happens
+; to also be described as a single slide, so this is testing that we
+; don't emit the zipodd instruction.
define <4 x i32> @zipodd_v4i32_single(<4 x i32> %a) {
; CHECK-LABEL: zipodd_v4i32_single:
; CHECK: # %bb.0: # %entry