Make non-affine statement names isl compatible

Named isl sets can generally have any name if they remain within Polly, but only
certain strings can be parsed by isl. The new names we create ensure that we
can always copy-past isl strings from Polly to other isl tools, e.g. for
debugging.

llvm-svn: 241787

16 files changed, 99 insertions, 97 deletions

diff --git a/polly/lib/Analysis/ScopInfo.cpp b/polly/lib/Analysis/ScopInfo.cpp
index 94e14fd..6ecedfa 100644
--- a/polly/lib/Analysis/ScopInfo.cpp
+++ b/polly/lib/Analysis/ScopInfo.cpp
@@ -1083,7 +1083,7 @@ ScopStmt::ScopStmt(Scop &parent, TempScop &tempScop, const Region &CurRegion,
   for (unsigned i = 0, e = Nest.size(); i < e; ++i)
     NestLoops[i] = Nest[i];
 
-  BaseName = getIslCompatibleName("Stmt_(", R.getNameStr(), ")");
+  BaseName = getIslCompatibleName("Stmt_", R.getNameStr(), "");
 
   Domain = buildDomain(tempScop, CurRegion);
   buildSchedule(ScheduleVec);
diff --git a/polly/lib/Support/GICHelper.cpp b/polly/lib/Support/GICHelper.cpp
index adb758c..c260767 100644
--- a/polly/lib/Support/GICHelper.cpp
+++ b/polly/lib/Support/GICHelper.cpp
@@ -134,6 +134,8 @@ static void replace(std::string &str, const std::string &find,
 static void makeIslCompatible(std::string &str) {
   replace(str, ".", "_");
   replace(str, "\"", "_");
+  replace(str, " ", "__");
+  replace(str, "=>", "TO");
 }
 
 std::string polly::getIslCompatibleName(const std::string &Prefix,
diff --git a/polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_1.ll b/polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_1.ll
index 4586ed5..ebc9a4ab 100644
--- a/polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_1.ll
+++ b/polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_1.ll
@@ -10,17 +10,17 @@
 ; SCALAR:    Alias Groups (0):
 ; SCALAR:        n/a
 ; SCALAR:    Statements {
-; SCALAR:      Stmt_(bb3 => bb11)
+; SCALAR:      Stmt_bb3__TO__bb11
 ; SCALAR:            Domain :=
-; SCALAR:                { Stmt_(bb3 => bb11)[i0] : i0 >= 0 and i0 <= 1023 };
+; SCALAR:                { Stmt_bb3__TO__bb11[i0] : i0 >= 0 and i0 <= 1023 };
 ; SCALAR:            Schedule :=
-; SCALAR:                { Stmt_(bb3 => bb11)[i0] -> [i0] };
+; SCALAR:                { Stmt_bb3__TO__bb11[i0] -> [i0] };
 ; SCALAR:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; SCALAR:                { Stmt_(bb3 => bb11)[i0] -> MemRef_C[i0] };
+; SCALAR:                { Stmt_bb3__TO__bb11[i0] -> MemRef_C[i0] };
 ; SCALAR:            ReadAccess := [Reduction Type: +] [Scalar: 0]
-; SCALAR:                { Stmt_(bb3 => bb11)[i0] -> MemRef_A[o0] : o0 <= 2147483645 and o0 >= -2147483648 };
+; SCALAR:                { Stmt_bb3__TO__bb11[i0] -> MemRef_A[o0] : o0 <= 2147483645 and o0 >= -2147483648 };
 ; SCALAR:            MayWriteAccess := [Reduction Type: +] [Scalar: 0]
-; SCALAR:                { Stmt_(bb3 => bb11)[i0] -> MemRef_A[o0] : o0 <= 2147483645 and o0 >= -2147483648 };
+; SCALAR:                { Stmt_bb3__TO__bb11[i0] -> MemRef_A[o0] : o0 <= 2147483645 and o0 >= -2147483648 };
 ; SCALAR:    }
 
 ;
diff --git a/polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_2.ll b/polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_2.ll
index 6ea874a..22d84d6 100644
--- a/polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_2.ll
+++ b/polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_2.ll
@@ -44,19 +44,19 @@
 ; ALL:    Alias Groups (0):
 ; ALL:        n/a
 ; ALL:    Statements {
-; ALL:      Stmt_(bb15 => bb25)
+; ALL:      Stmt_bb15__TO__bb25
 ; ALL:            Domain :=
-; ALL:                { Stmt_(bb15 => bb25)[i0, i1] : i0 >= 0 and i0 <= 1023 and i1 >= 0 and i1 <= 1023 };
+; ALL:                { Stmt_bb15__TO__bb25[i0, i1] : i0 >= 0 and i0 <= 1023 and i1 >= 0 and i1 <= 1023 };
 ; ALL:            Schedule :=
-; ALL:                { Stmt_(bb15 => bb25)[i0, i1] -> [i0, i1] };
+; ALL:                { Stmt_bb15__TO__bb25[i0, i1] -> [i0, i1] };
 ; ALL:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; ALL:                { Stmt_(bb15 => bb25)[i0, i1] -> MemRef_A[i0] };
+; ALL:                { Stmt_bb15__TO__bb25[i0, i1] -> MemRef_A[i0] };
 ; ALL:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; ALL:                { Stmt_(bb15 => bb25)[i0, i1] -> MemRef_A[i1] };
+; ALL:                { Stmt_bb15__TO__bb25[i0, i1] -> MemRef_A[i1] };
 ; ALL:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; ALL:                { Stmt_(bb15 => bb25)[i0, i1] -> MemRef_A[o0] : o0 <= 2305843009213693949 and o0 >= 0 };
+; ALL:                { Stmt_bb15__TO__bb25[i0, i1] -> MemRef_A[o0] : o0 <= 2305843009213693949 and o0 >= 0 };
 ; ALL:            MayWriteAccess := [Reduction Type: NONE] [Scalar: 0]
-; ALL:                { Stmt_(bb15 => bb25)[i0, i1] -> MemRef_A[o0] : o0 <= 2305843009213693949 and o0 >= 0 };
+; ALL:                { Stmt_bb15__TO__bb25[i0, i1] -> MemRef_A[o0] : o0 <= 2305843009213693949 and o0 >= 0 };
 ; ALL:    }
 ;
 ;    void f(int *A) {
diff --git a/polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_3.ll b/polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_3.ll
index d363089..bbcc9ee 100644
--- a/polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_3.ll
+++ b/polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_3.ll
@@ -46,19 +46,19 @@
 ; ALL:    Alias Groups (0):
 ; ALL:        n/a
 ; ALL:    Statements {
-; ALL:      Stmt_(bb15 => bb25)
+; ALL:      Stmt_bb15__TO__bb25
 ; ALL:            Domain :=
-; ALL:                { Stmt_(bb15 => bb25)[i0, i1] : i0 >= 0 and i0 <= 1023 and i1 >= 0 and i1 <= 1023 };
+; ALL:                { Stmt_bb15__TO__bb25[i0, i1] : i0 >= 0 and i0 <= 1023 and i1 >= 0 and i1 <= 1023 };
 ; ALL:            Schedule :=
-; ALL:                { Stmt_(bb15 => bb25)[i0, i1] -> [i0, i1] };
+; ALL:                { Stmt_bb15__TO__bb25[i0, i1] -> [i0, i1] };
 ; ALL:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; ALL:                { Stmt_(bb15 => bb25)[i0, i1] -> MemRef_A[i0] };
+; ALL:                { Stmt_bb15__TO__bb25[i0, i1] -> MemRef_A[i0] };
 ; ALL:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; ALL:                { Stmt_(bb15 => bb25)[i0, i1] -> MemRef_A[i1] };
+; ALL:                { Stmt_bb15__TO__bb25[i0, i1] -> MemRef_A[i1] };
 ; ALL:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; ALL:                { Stmt_(bb15 => bb25)[i0, i1] -> MemRef_A[o0] : o0 <= 4294967293 and o0 >= 0 };
+; ALL:                { Stmt_bb15__TO__bb25[i0, i1] -> MemRef_A[o0] : o0 <= 4294967293 and o0 >= 0 };
 ; ALL:            MayWriteAccess := [Reduction Type: NONE] [Scalar: 0]
-; ALL:                { Stmt_(bb15 => bb25)[i0, i1] -> MemRef_A[o0] : o0 <= 4294967293 and o0 >= 0 };
+; ALL:                { Stmt_bb15__TO__bb25[i0, i1] -> MemRef_A[o0] : o0 <= 4294967293 and o0 >= 0 };
 ; ALL:    }
 ;
 ;    void f(int *A) {
diff --git a/polly/test/ScopInfo/NonAffine/non_affine_conditional_nested.ll b/polly/test/ScopInfo/NonAffine/non_affine_conditional_nested.ll
index baddf03..4983c09d 100644
--- a/polly/test/ScopInfo/NonAffine/non_affine_conditional_nested.ll
+++ b/polly/test/ScopInfo/NonAffine/non_affine_conditional_nested.ll
@@ -10,19 +10,19 @@
 ; CHECK:    Region: %bb1---%bb18
 ; CHECK:    Max Loop Depth:  1
 ; CHECK:    Statements {
-; CHECK:      Stmt_(bb2 => bb16)
+; CHECK:      Stmt_bb2__TO__bb16
 ; CHECK:            Domain :=
-; CHECK:                { Stmt_(bb2 => bb16)[i0] : i0 >= 0 and i0 <= 1023 };
+; CHECK:                { Stmt_bb2__TO__bb16[i0] : i0 >= 0 and i0 <= 1023 };
 ; CHECK:            Schedule :=
-; CHECK:                { Stmt_(bb2 => bb16)[i0] -> [i0] };
+; CHECK:                { Stmt_bb2__TO__bb16[i0] -> [i0] };
 ; CHECK:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; CHECK:                { Stmt_(bb2 => bb16)[i0] -> MemRef_A[i0] };
+; CHECK:                { Stmt_bb2__TO__bb16[i0] -> MemRef_A[i0] };
 ; CHECK:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; CHECK:                { Stmt_(bb2 => bb16)[i0] -> MemRef_A[-1 + i0] };
+; CHECK:                { Stmt_bb2__TO__bb16[i0] -> MemRef_A[-1 + i0] };
 ; CHECK:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; CHECK:                { Stmt_(bb2 => bb16)[i0] -> MemRef_A[-2 + i0] };
+; CHECK:                { Stmt_bb2__TO__bb16[i0] -> MemRef_A[-2 + i0] };
 ; CHECK:            MayWriteAccess :=  [Reduction Type: NONE] [Scalar: 0]
-; CHECK:                { Stmt_(bb2 => bb16)[i0] -> MemRef_A[i0] };
+; CHECK:                { Stmt_bb2__TO__bb16[i0] -> MemRef_A[i0] };
 ; CHECK:    }
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/polly/test/ScopInfo/NonAffine/non_affine_conditional_surrounding_affine_loop.ll b/polly/test/ScopInfo/NonAffine/non_affine_conditional_surrounding_affine_loop.ll
index 44dd738..0a5a58b 100644
--- a/polly/test/ScopInfo/NonAffine/non_affine_conditional_surrounding_affine_loop.ll
+++ b/polly/test/ScopInfo/NonAffine/non_affine_conditional_surrounding_affine_loop.ll
@@ -33,17 +33,17 @@
 ; ALL:    Alias Groups (0):
 ; ALL:        n/a
 ; ALL:    Statements {
-; ALL:      Stmt_(bb4 => bb17)
+; ALL:      Stmt_bb4__TO__bb17
 ; ALL:            Domain :=
-; ALL:                { Stmt_(bb4 => bb17)[i0] : i0 >= 0 and i0 <= 1023 };
+; ALL:                { Stmt_bb4__TO__bb17[i0] : i0 >= 0 and i0 <= 1023 };
 ; ALL:            Schedule :=
-; ALL:                { Stmt_(bb4 => bb17)[i0] -> [i0] };
+; ALL:                { Stmt_bb4__TO__bb17[i0] -> [i0] };
 ; ALL:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; ALL:                { Stmt_(bb4 => bb17)[i0] -> MemRef_A[i0] };
+; ALL:                { Stmt_bb4__TO__bb17[i0] -> MemRef_A[i0] };
 ; ALL:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; ALL:                { Stmt_(bb4 => bb17)[i0] -> MemRef_A[o0] : o0 <= 2147483645 and o0 >= 0 };
+; ALL:                { Stmt_bb4__TO__bb17[i0] -> MemRef_A[o0] : o0 <= 2147483645 and o0 >= 0 };
 ; ALL:            MayWriteAccess := [Reduction Type: NONE] [Scalar: 0]
-; ALL:                { Stmt_(bb4 => bb17)[i0] -> MemRef_A[o0] : o0 <= 2147483645 and o0 >= 0 };
+; ALL:                { Stmt_bb4__TO__bb17[i0] -> MemRef_A[o0] : o0 <= 2147483645 and o0 >= 0 };
 ; ALL:    }
 ;
 ;    void f(int *A, int N) {
diff --git a/polly/test/ScopInfo/NonAffine/non_affine_conditional_surrounding_non_affine_loop.ll b/polly/test/ScopInfo/NonAffine/non_affine_conditional_surrounding_non_affine_loop.ll
index cc57440..fb70f07 100644
--- a/polly/test/ScopInfo/NonAffine/non_affine_conditional_surrounding_non_affine_loop.ll
+++ b/polly/test/ScopInfo/NonAffine/non_affine_conditional_surrounding_non_affine_loop.ll
@@ -33,17 +33,17 @@
 ; ALL:    Alias Groups (0):
 ; ALL:        n/a
 ; ALL:    Statements {
-; ALL:      Stmt_(bb4 => bb18)
+; ALL:      Stmt_bb4__TO__bb18
 ; ALL:            Domain :=
-; ALL:                { Stmt_(bb4 => bb18)[i0] : i0 >= 0 and i0 <= 1023 };
+; ALL:                { Stmt_bb4__TO__bb18[i0] : i0 >= 0 and i0 <= 1023 };
 ; ALL:            Schedule :=
-; ALL:                { Stmt_(bb4 => bb18)[i0] -> [i0] };
+; ALL:                { Stmt_bb4__TO__bb18[i0] -> [i0] };
 ; ALL:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; ALL:                { Stmt_(bb4 => bb18)[i0] -> MemRef_A[i0] };
+; ALL:                { Stmt_bb4__TO__bb18[i0] -> MemRef_A[i0] };
 ; ALL:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; ALL:                { Stmt_(bb4 => bb18)[i0] -> MemRef_A[o0] : o0 <= 2199023254526 and o0 >= 0 };
+; ALL:                { Stmt_bb4__TO__bb18[i0] -> MemRef_A[o0] : o0 <= 2199023254526 and o0 >= 0 };
 ; ALL:            MayWriteAccess := [Reduction Type: NONE] [Scalar: 0]
-; ALL:                { Stmt_(bb4 => bb18)[i0] -> MemRef_A[o0] : o0 <= 2199023254526 and o0 >= 0 };
+; ALL:                { Stmt_bb4__TO__bb18[i0] -> MemRef_A[o0] : o0 <= 2199023254526 and o0 >= 0 };
 ; ALL:    }
 ;
 ;    void f(int *A, int N) {
diff --git a/polly/test/ScopInfo/NonAffine/non_affine_float_compare.ll b/polly/test/ScopInfo/NonAffine/non_affine_float_compare.ll
index f55334c..f473d4b 100644
--- a/polly/test/ScopInfo/NonAffine/non_affine_float_compare.ll
+++ b/polly/test/ScopInfo/NonAffine/non_affine_float_compare.ll
@@ -10,19 +10,19 @@
 ; CHECK:    Region: %bb1---%bb14
 ; CHECK:    Max Loop Depth:  1
 ; CHECK:    Statements {
-; CHECK:      Stmt_(bb2 => bb12)
+; CHECK:      Stmt_bb2__TO__bb12
 ; CHECK:            Domain :=
-; CHECK:                { Stmt_(bb2 => bb12)[i0] : i0 >= 0 and i0 <= 1023 };
+; CHECK:                { Stmt_bb2__TO__bb12[i0] : i0 >= 0 and i0 <= 1023 };
 ; CHECK:            Schedule :=
-; CHECK:                { Stmt_(bb2 => bb12)[i0] -> [i0] };
+; CHECK:                { Stmt_bb2__TO__bb12[i0] -> [i0] };
 ; CHECK:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; CHECK:                { Stmt_(bb2 => bb12)[i0] -> MemRef_A[i0] };
+; CHECK:                { Stmt_bb2__TO__bb12[i0] -> MemRef_A[i0] };
 ; CHECK:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; CHECK:                { Stmt_(bb2 => bb12)[i0] -> MemRef_A[-1 + i0] };
+; CHECK:                { Stmt_bb2__TO__bb12[i0] -> MemRef_A[-1 + i0] };
 ; CHECK:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; CHECK:                { Stmt_(bb2 => bb12)[i0] -> MemRef_A[i0] };
+; CHECK:                { Stmt_bb2__TO__bb12[i0] -> MemRef_A[i0] };
 ; CHECK:            MayWriteAccess :=  [Reduction Type: NONE] [Scalar: 0]
-; CHECK:                { Stmt_(bb2 => bb12)[i0] -> MemRef_A[i0] };
+; CHECK:                { Stmt_bb2__TO__bb12[i0] -> MemRef_A[i0] };
 ; CHECK:    }
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 
diff --git a/polly/test/ScopInfo/NonAffine/non_affine_loop_condition.ll b/polly/test/ScopInfo/NonAffine/non_affine_loop_condition.ll
index b64b784..66c41ef 100644
--- a/polly/test/ScopInfo/NonAffine/non_affine_loop_condition.ll
+++ b/polly/test/ScopInfo/NonAffine/non_affine_loop_condition.ll
@@ -11,17 +11,17 @@
 ; CHECK:    Region: %bb1---%bb12
 ; CHECK:    Max Loop Depth:  1
 ; CHECK:    Statements {
-; CHECK:      Stmt_(bb3 => bb10)
+; CHECK:      Stmt_bb3__TO__bb10
 ; CHECK:            Domain :=
-; CHECK:                { Stmt_(bb3 => bb10)[i0] : i0 >= 0 and i0 <= 1023 };
+; CHECK:                { Stmt_bb3__TO__bb10[i0] : i0 >= 0 and i0 <= 1023 };
 ; CHECK:            Schedule :=
-; CHECK:                { Stmt_(bb3 => bb10)[i0] -> [i0] };
+; CHECK:                { Stmt_bb3__TO__bb10[i0] -> [i0] };
 ; CHECK:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; CHECK:                { Stmt_(bb3 => bb10)[i0] -> MemRef_C[i0] };
+; CHECK:                { Stmt_bb3__TO__bb10[i0] -> MemRef_C[i0] };
 ; CHECK:            ReadAccess := [Reduction Type: +] [Scalar: 0]
-; CHECK:                { Stmt_(bb3 => bb10)[i0] -> MemRef_A[i0] };
+; CHECK:                { Stmt_bb3__TO__bb10[i0] -> MemRef_A[i0] };
 ; CHECK:            MayWriteAccess :=  [Reduction Type: +] [Scalar: 0]
-; CHECK:                { Stmt_(bb3 => bb10)[i0] -> MemRef_A[i0] };
+; CHECK:                { Stmt_bb3__TO__bb10[i0] -> MemRef_A[i0] };
 ; CHECK:    }
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/polly/test/ScopInfo/NonAffine/non_affine_loop_used_later.ll b/polly/test/ScopInfo/NonAffine/non_affine_loop_used_later.ll
index 7fb2bc9..a58918f 100644
--- a/polly/test/ScopInfo/NonAffine/non_affine_loop_used_later.ll
+++ b/polly/test/ScopInfo/NonAffine/non_affine_loop_used_later.ll
@@ -23,25 +23,25 @@
 ; CHECK:                [N] -> { Stmt_bb2[i0] -> MemRef_j_0[] };
 ; CHECK:            MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 1]
 ; CHECK:                [N] -> { Stmt_bb2[i0] -> MemRef_j_0[] };
-; CHECK:      Stmt_(bb4 => bb18)
+; CHECK:      Stmt_bb4__TO__bb18
 ; CHECK:            Domain :=
-; CHECK:                [N] -> { Stmt_(bb4 => bb18)[i0] : i0 >= 0 and N >= 1 and i0 <= -1 + N };
+; CHECK:                [N] -> { Stmt_bb4__TO__bb18[i0] : i0 >= 0 and N >= 1 and i0 <= -1 + N };
 ; CHECK:            Schedule :=
-; CHECK:                [N] -> { Stmt_(bb4 => bb18)[i0] -> [i0, 1] };
+; CHECK:                [N] -> { Stmt_bb4__TO__bb18[i0] -> [i0, 1] };
 ; CHECK:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; CHECK:                [N] -> { Stmt_(bb4 => bb18)[i0] -> MemRef_A[i0] };
+; CHECK:                [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_A[i0] };
 ; CHECK:            ReadAccess := [Reduction Type: NONE] [Scalar: 1]
-; CHECK:                [N] -> { Stmt_(bb4 => bb18)[i0] -> MemRef_j_0[] };
+; CHECK:                [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_j_0[] };
 ; CHECK:            MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 1]
-; CHECK:                [N] -> { Stmt_(bb4 => bb18)[i0] -> MemRef_j_2[] };
+; CHECK:                [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_j_2[] };
 ; CHECK:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; CHECK:                [N] -> { Stmt_(bb4 => bb18)[i0] -> MemRef_A[i0] };
+; CHECK:                [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_A[i0] };
 ; CHECK:            MayWriteAccess := [Reduction Type: NONE] [Scalar: 0]
-; CHECK:                [N] -> { Stmt_(bb4 => bb18)[i0] -> MemRef_A[i0] };
+; CHECK:                [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_A[i0] };
 ; CHECK:            ReadAccess := [Reduction Type: NONE] [Scalar: 1]
-; CHECK:                [N] -> { Stmt_(bb4 => bb18)[i0] -> MemRef_smax[] };
+; CHECK:                [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_smax[] };
 ; CHECK:            MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
-; CHECK:                [N] -> { Stmt_(bb4 => bb18)[i0] -> MemRef_j_2[] };
+; CHECK:                [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_j_2[] };
 ; CHECK:      Stmt_bb18
 ; CHECK:            Domain :=
 ; CHECK:                [N] -> { Stmt_bb18[i0] : i0 >= 0 and N >= 1 and i0 <= -1 + N };
diff --git a/polly/test/ScopInfo/no-scalar-deps-in-non-affine-subregion.ll b/polly/test/ScopInfo/no-scalar-deps-in-non-affine-subregion.ll
index 9bc57d2..7e71189 100644
--- a/polly/test/ScopInfo/no-scalar-deps-in-non-affine-subregion.ll
+++ b/polly/test/ScopInfo/no-scalar-deps-in-non-affine-subregion.ll
@@ -4,7 +4,7 @@
 ; defined and used on the non-affine subregion only, thus we do not need
 ; to represent the definition and uses in the model.
 ;
-; CHECK:          Stmt_(bb2 => bb11)
+; CHECK:          Stmt_bb2__TO__bb11
 ; CHECK-NOT:        [Scalar: 1]
 ; CHECK-NOT:        MemRef_x
 ;
diff --git a/polly/test/ScopInfo/non_affine_region_1.ll b/polly/test/ScopInfo/non_affine_region_1.ll
index e958e75..8e8752e 100644
--- a/polly/test/ScopInfo/non_affine_region_1.ll
+++ b/polly/test/ScopInfo/non_affine_region_1.ll
@@ -28,13 +28,13 @@
 ; CHECK:       Stmt_bb8
 ; CHECK:             MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 1]
 ; CHECK:                 [b] -> { Stmt_bb8[i0] -> MemRef_x_1[] };
-; CHECK:       Stmt_(bb10 => bb18)
+; CHECK:       Stmt_bb10__TO__bb18
 ; CHECK-NEXT:        Domain :=
-; CHECK-NEXT:            [b] -> { Stmt_(bb10 => bb18)[i0] : i0 >= 0 and i0 <= 1023 };
+; CHECK-NEXT:            [b] -> { Stmt_bb10__TO__bb18[i0] : i0 >= 0 and i0 <= 1023 };
 ; CHECK-NEXT:        Schedule :=
-; CHECK-NEXT:            [b] -> { Stmt_(bb10 => bb18)[i0] -> [i0, 3] };
+; CHECK-NEXT:            [b] -> { Stmt_bb10__TO__bb18[i0] -> [i0, 3] };
 ; CHECK-NEXT:        ReadAccess := [Reduction Type: NONE] [Scalar: 1]
-; CHECK-NEXT:            [b] -> { Stmt_(bb10 => bb18)[i0] -> MemRef_x_1[] }
+; CHECK-NEXT:            [b] -> { Stmt_bb10__TO__bb18[i0] -> MemRef_x_1[] }
 ; CHECK-NOT:   [Scalar: 1]
 ;
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/polly/test/ScopInfo/non_affine_region_2.ll b/polly/test/ScopInfo/non_affine_region_2.ll
index 29163d0..b572bd4 100644
--- a/polly/test/ScopInfo/non_affine_region_2.ll
+++ b/polly/test/ScopInfo/non_affine_region_2.ll
@@ -20,25 +20,25 @@
 ;    }
 ;
 ; CHECK: Region: %bb2---%bb21
-; CHECK:   Stmt_(bb3 => bb18)
+; CHECK:   Stmt_bb3__TO__bb18
 ; CHECK:         Domain :=
-; CHECK:             { Stmt_(bb3 => bb18)[i0] : i0 >= 0 and i0 <= 1023 };
+; CHECK:             { Stmt_bb3__TO__bb18[i0] : i0 >= 0 and i0 <= 1023 };
 ; CHECK:         Schedule :=
-; CHECK:             { Stmt_(bb3 => bb18)[i0] -> [i0, 0] };
-; CHECK-NOT:         { Stmt_(bb3 => bb18)[i0] -> MemRef_x_0[] };
-; CHECK-NOT:         { Stmt_(bb3 => bb18)[i0] -> MemRef_x_1[] };
+; CHECK:             { Stmt_bb3__TO__bb18[i0] -> [i0, 0] };
+; CHECK-NOT:         { Stmt_bb3__TO__bb18[i0] -> MemRef_x_0[] };
+; CHECK-NOT:         { Stmt_bb3__TO__bb18[i0] -> MemRef_x_1[] };
 ; CHECK:         ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; CHECK-NEXT:        { Stmt_(bb3 => bb18)[i0] -> MemRef_A[i0] };
-; CHECK-NOT:         { Stmt_(bb3 => bb18)[i0] -> MemRef_x_0[] };
-; CHECK-NOT:         { Stmt_(bb3 => bb18)[i0] -> MemRef_x_1[] };
+; CHECK-NEXT:        { Stmt_bb3__TO__bb18[i0] -> MemRef_A[i0] };
+; CHECK-NOT:         { Stmt_bb3__TO__bb18[i0] -> MemRef_x_0[] };
+; CHECK-NOT:         { Stmt_bb3__TO__bb18[i0] -> MemRef_x_1[] };
 ; CHECK:         MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 1]
-; CHECK-NEXT:        { Stmt_(bb3 => bb18)[i0] -> MemRef_x_2[] };
-; CHECK-NOT:         { Stmt_(bb3 => bb18)[i0] -> MemRef_x_0[] };
-; CHECK-NOT:         { Stmt_(bb3 => bb18)[i0] -> MemRef_x_1[] };
+; CHECK-NEXT:        { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2[] };
+; CHECK-NOT:         { Stmt_bb3__TO__bb18[i0] -> MemRef_x_0[] };
+; CHECK-NOT:         { Stmt_bb3__TO__bb18[i0] -> MemRef_x_1[] };
 ; CHECK:         MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
-; CHECK-NEXT:        { Stmt_(bb3 => bb18)[i0] -> MemRef_x_2[] };
-; CHECK-NOT:         { Stmt_(bb3 => bb18)[i0] -> MemRef_x_0[] };
-; CHECK-NOT:         { Stmt_(bb3 => bb18)[i0] -> MemRef_x_1[] };
+; CHECK-NEXT:        { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2[] };
+; CHECK-NOT:         { Stmt_bb3__TO__bb18[i0] -> MemRef_x_0[] };
+; CHECK-NOT:         { Stmt_bb3__TO__bb18[i0] -> MemRef_x_1[] };
 ; CHECK:   Stmt_bb18
 ; CHECK:         Domain :=
 ; CHECK:             { Stmt_bb18[i0] : i0 >= 0 and i0 <= 1023 };
diff --git a/polly/test/ScopInfo/non_affine_region_3.ll b/polly/test/ScopInfo/non_affine_region_3.ll
index e145682..0ca2191 100644
--- a/polly/test/ScopInfo/non_affine_region_3.ll
+++ b/polly/test/ScopInfo/non_affine_region_3.ll
@@ -20,21 +20,21 @@
 ;    }
 ;
 ; CHECK: Region: %bb2---%bb21
-; CHECK:   Stmt_(bb3 => bb18)
+; CHECK:   Stmt_bb3__TO__bb18
 ; CHECK:         Domain :=
-; CHECK:             { Stmt_(bb3 => bb18)[i0] : i0 >= 0 and i0 <= 1023 };
+; CHECK:             { Stmt_bb3__TO__bb18[i0] : i0 >= 0 and i0 <= 1023 };
 ; CHECK:         Schedule :=
-; CHECK:             { Stmt_(bb3 => bb18)[i0] -> [i0, 0] };
+; CHECK:             { Stmt_bb3__TO__bb18[i0] -> [i0, 0] };
 ; CHECK:         ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; CHECK:             { Stmt_(bb3 => bb18)[i0] -> MemRef_A[i0] };
+; CHECK:             { Stmt_bb3__TO__bb18[i0] -> MemRef_A[i0] };
 ; CHECK:         MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 1]
-; CHECK:             { Stmt_(bb3 => bb18)[i0] -> MemRef_x_2[] };
+; CHECK:             { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2[] };
 ; CHECK:         MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
-; CHECK:             { Stmt_(bb3 => bb18)[i0] -> MemRef_x_2[] };
+; CHECK:             { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2[] };
 ; CHECK:         MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
-; CHECK:             { Stmt_(bb3 => bb18)[i0] -> MemRef_x_2[] };
+; CHECK:             { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2[] };
 ; CHECK:         MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
-; CHECK:             { Stmt_(bb3 => bb18)[i0] -> MemRef_x_2[] };
+; CHECK:             { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2[] };
 ; CHECK:   Stmt_bb18
 ; CHECK:         Domain :=
 ; CHECK:             { Stmt_bb18[i0] : i0 >= 0 and i0 <= 1023 };
diff --git a/polly/test/ScopInfo/non_affine_region_4.ll b/polly/test/ScopInfo/non_affine_region_4.ll
index 96b9d91..9052c4d 100644
--- a/polly/test/ScopInfo/non_affine_region_4.ll
+++ b/polly/test/ScopInfo/non_affine_region_4.ll
@@ -13,19 +13,19 @@
 ;    }
 ;
 ; CHECK:    Region: %bb1---%bb11
-; CHECK:      Stmt_(bb2 => bb7)
+; CHECK:      Stmt_bb2__TO__bb7
 ; CHECK:            Domain :=
-; CHECK:                { Stmt_(bb2 => bb7)[i0] : i0 >= 0 and i0 <= 1023 };
+; CHECK:                { Stmt_bb2__TO__bb7[i0] : i0 >= 0 and i0 <= 1023 };
 ; CHECK:            Schedule :=
-; CHECK:                { Stmt_(bb2 => bb7)[i0] -> [i0, 0] };
+; CHECK:                { Stmt_bb2__TO__bb7[i0] -> [i0, 0] };
 ; CHECK:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; CHECK:                { Stmt_(bb2 => bb7)[i0] -> MemRef_A[i0] };
+; CHECK:                { Stmt_bb2__TO__bb7[i0] -> MemRef_A[i0] };
 ; CHECK:            MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 1]
-; CHECK:                { Stmt_(bb2 => bb7)[i0] -> MemRef_x[] };
+; CHECK:                { Stmt_bb2__TO__bb7[i0] -> MemRef_x[] };
 ; CHECK:            MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 1]
-; CHECK:                { Stmt_(bb2 => bb7)[i0] -> MemRef_y[] };
+; CHECK:                { Stmt_bb2__TO__bb7[i0] -> MemRef_y[] };
 ; CHECK:            MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
-; CHECK:                { Stmt_(bb2 => bb7)[i0] -> MemRef_y[] };
+; CHECK:                { Stmt_bb2__TO__bb7[i0] -> MemRef_y[] };
 ; CHECK:      Stmt_bb7
 ; CHECK:            Domain :=
 ; CHECK:                { Stmt_bb7[i0] : i0 >= 0 and i0 <= 1023 };