[X86] Remove FeatureRTM from Skylake processor list

Summary:
There are a LOT of Skylakes and later without TSX-NI. Examples:
- SKL: https://ark.intel.com/products/136863/Intel-Core-i3-8121U-Processor-4M-Cache-up-to-3-20-GHz-
- KBL: https://ark.intel.com/products/97540/Intel-Core-i7-7560U-Processor-4M-Cache-up-to-3-80-GHz-
- KBL-R: https://ark.intel.com/products/149091/Intel-Core-i7-8565U-Processor-8M-Cache-up-to-4-60-GHz-
- CNL: https://ark.intel.com/products/136863/Intel-Core-i3-8121U-Processor-4M-Cache-up-to-3_20-GHz

This feature seems to be present only on high-end desktop and server
chips (I can't find any SKX without). This commit leaves it disabled
for all processors, but can be re-enabled for specific builds with
-mrtm.

Matches https://reviews.llvm.org/D53041

Patch by Thiago Macieira

Reviewers: erichkeane, craig.topper

Reviewed By: craig.topper

Subscribers: lebedev.ri, cfe-commits

Differential Revision: https://reviews.llvm.org/D53042

llvm-svn: 344117

2 files changed, 0 insertions, 15 deletions

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index b986ea3..1223e86 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -169,7 +169,6 @@ bool X86TargetInfo::initFeatureMap(
     if (Kind != CK_SkylakeServer) // SKX inherits all SKL features, except SGX
       setFeatureEnabledImpl(Features, "sgx", true);
     setFeatureEnabledImpl(Features, "clflushopt", true);
-    setFeatureEnabledImpl(Features, "rtm", true);
     setFeatureEnabledImpl(Features, "aes", true);
     LLVM_FALLTHROUGH;
   case CK_Broadwell:
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c
index df61a65..c70ebf3 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -670,7 +670,6 @@
 // CHECK_SKL_M32: #define __PRFCHW__ 1
 // CHECK_SKL_M32: #define __RDRND__ 1
 // CHECK_SKL_M32: #define __RDSEED__ 1
-// CHECK_SKL_M32: #define __RTM__ 1
 // CHECK_SKL_M32: #define __SGX__ 1
 // CHECK_SKL_M32: #define __SSE2__ 1
 // CHECK_SKL_M32: #define __SSE3__ 1
@@ -706,7 +705,6 @@
 // CHECK_SKL_M64: #define __PRFCHW__ 1
 // CHECK_SKL_M64: #define __RDRND__ 1
 // CHECK_SKL_M64: #define __RDSEED__ 1
-// CHECK_SKL_M64: #define __RTM__ 1
 // CHECK_SKL_M64: #define __SGX__ 1
 // CHECK_SKL_M64: #define __SSE2_MATH__ 1
 // CHECK_SKL_M64: #define __SSE2__ 1
@@ -747,7 +745,6 @@
 // CHECK_KNL_M32: #define __PREFETCHWT1__ 1
 // CHECK_KNL_M32: #define __PRFCHW__ 1
 // CHECK_KNL_M32: #define __RDRND__ 1
-// CHECK_KNL_M32: #define __RTM__ 1
 // CHECK_KNL_M32: #define __SSE2__ 1
 // CHECK_KNL_M32: #define __SSE3__ 1
 // CHECK_KNL_M32: #define __SSE4_1__ 1
@@ -785,7 +782,6 @@
 // CHECK_KNL_M64: #define __PREFETCHWT1__ 1
 // CHECK_KNL_M64: #define __PRFCHW__ 1
 // CHECK_KNL_M64: #define __RDRND__ 1
-// CHECK_KNL_M64: #define __RTM__ 1
 // CHECK_KNL_M64: #define __SSE2_MATH__ 1
 // CHECK_KNL_M64: #define __SSE2__ 1
 // CHECK_KNL_M64: #define __SSE3__ 1
@@ -827,7 +823,6 @@
 // CHECK_KNM_M32: #define __PREFETCHWT1__ 1
 // CHECK_KNM_M32: #define __PRFCHW__ 1
 // CHECK_KNM_M32: #define __RDRND__ 1
-// CHECK_KNM_M32: #define __RTM__ 1
 // CHECK_KNM_M32: #define __SSE2__ 1
 // CHECK_KNM_M32: #define __SSE3__ 1
 // CHECK_KNM_M32: #define __SSE4_1__ 1
@@ -863,7 +858,6 @@
 // CHECK_KNM_M64: #define __PREFETCHWT1__ 1
 // CHECK_KNM_M64: #define __PRFCHW__ 1
 // CHECK_KNM_M64: #define __RDRND__ 1
-// CHECK_KNM_M64: #define __RTM__ 1
 // CHECK_KNM_M64: #define __SSE2_MATH__ 1
 // CHECK_KNM_M64: #define __SSE2__ 1
 // CHECK_KNM_M64: #define __SSE3__ 1
@@ -907,7 +901,6 @@
 // CHECK_SKX_M32: #define __PRFCHW__ 1
 // CHECK_SKX_M32: #define __RDRND__ 1
 // CHECK_SKX_M32: #define __RDSEED__ 1
-// CHECK_SKX_M32: #define __RTM__ 1
 // CHECK_SKX_M32-NOT: #define __SGX__ 1
 // CHECK_SKX_M32: #define __SSE2__ 1
 // CHECK_SKX_M32: #define __SSE3__ 1
@@ -954,7 +947,6 @@
 // CHECK_SKX_M64: #define __PRFCHW__ 1
 // CHECK_SKX_M64: #define __RDRND__ 1
 // CHECK_SKX_M64: #define __RDSEED__ 1
-// CHECK_SKX_M64: #define __RTM__ 1
 // CHECK_SKX_M64-NOT: #define __SGX__ 1
 // CHECK_SKX_M64: #define __SSE2_MATH__ 1
 // CHECK_SKX_M64: #define __SSE2__ 1
@@ -1006,7 +998,6 @@
 // CHECK_CNL_M32: #define __PRFCHW__ 1
 // CHECK_CNL_M32: #define __RDRND__ 1
 // CHECK_CNL_M32: #define __RDSEED__ 1
-// CHECK_CNL_M32: #define __RTM__ 1
 // CHECK_CNL_M32: #define __SGX__ 1
 // CHECK_CNL_M32: #define __SHA__ 1
 // CHECK_CNL_M32: #define __SSE2__ 1
@@ -1056,7 +1047,6 @@
 // CHECK_CNL_M64: #define __PRFCHW__ 1
 // CHECK_CNL_M64: #define __RDRND__ 1
 // CHECK_CNL_M64: #define __RDSEED__ 1
-// CHECK_CNL_M64: #define __RTM__ 1
 // CHECK_CNL_M64: #define __SGX__ 1
 // CHECK_CNL_M64: #define __SHA__ 1
 // CHECK_CNL_M64: #define __SSE2__ 1
@@ -1113,7 +1103,6 @@
 // CHECK_ICL_M32: #define __RDPID__ 1
 // CHECK_ICL_M32: #define __RDRND__ 1
 // CHECK_ICL_M32: #define __RDSEED__ 1
-// CHECK_ICL_M32: #define __RTM__ 1
 // CHECK_ICL_M32: #define __SGX__ 1
 // CHECK_ICL_M32: #define __SHA__ 1
 // CHECK_ICL_M32: #define __SSE2__ 1
@@ -1172,7 +1161,6 @@
 // CHECK_ICL_M64: #define __RDPID__ 1
 // CHECK_ICL_M64: #define __RDRND__ 1
 // CHECK_ICL_M64: #define __RDSEED__ 1
-// CHECK_ICL_M64: #define __RTM__ 1
 // CHECK_ICL_M64: #define __SGX__ 1
 // CHECK_ICL_M64: #define __SHA__ 1
 // CHECK_ICL_M64: #define __SSE2__ 1
@@ -1233,7 +1221,6 @@
 // CHECK_ICX_M32: #define __RDPID__ 1
 // CHECK_ICX_M32: #define __RDRND__ 1
 // CHECK_ICX_M32: #define __RDSEED__ 1
-// CHECK_ICX_M32: #define __RTM__ 1
 // CHECK_ICX_M32: #define __SGX__ 1
 // CHECK_ICX_M32: #define __SHA__ 1
 // CHECK_ICX_M32: #define __SSE2__ 1
@@ -1293,7 +1280,6 @@
 // CHECK_ICX_M64: #define __RDPID__ 1
 // CHECK_ICX_M64: #define __RDRND__ 1
 // CHECK_ICX_M64: #define __RDSEED__ 1
-// CHECK_ICX_M64: #define __RTM__ 1
 // CHECK_ICX_M64: #define __SGX__ 1
 // CHECK_ICX_M64: #define __SHA__ 1
 // CHECK_ICX_M64: #define __SSE2__ 1