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| author | Craig Topper <craig.topper@sifive.com> | 2025-02-05 14:49:01 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-02-05 14:49:01 -0800 |
| commit | 0d7ee520d3a9b8997adf8eaaa22b33db9659d94e (patch) | |
| tree | 43ac9a0ff662cc131da49aefc3aef87eeeeb87db | |
| parent | de7be32734dc789ba35602a58f37a14f764ebd58 (diff) | |
| download | llvm-0d7ee520d3a9b8997adf8eaaa22b33db9659d94e.zip llvm-0d7ee520d3a9b8997adf8eaaa22b33db9659d94e.tar.gz llvm-0d7ee520d3a9b8997adf8eaaa22b33db9659d94e.tar.bz2 | |
[RISCV] Use getSignedConstant for negative values. (#125903)
The APInt constructor asserts if bits are set past the size of the APInt
unless it is signed. This currently fails on RV32 because more than XLen
bits are set.
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll | 1 |
3 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index ddda844..0284099 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -16353,7 +16353,7 @@ static SDValue performVP_REVERSECombine(SDNode *N, SelectionDAG &DAG, SDValue Temp2 = DAG.getNode(ISD::MUL, DL, XLenVT, Temp1, DAG.getConstant(ElemWidthByte, DL, XLenVT)); SDValue Base = DAG.getNode(ISD::ADD, DL, XLenVT, VPLoad->getBasePtr(), Temp2); - SDValue Stride = DAG.getConstant(-ElemWidthByte, DL, XLenVT); + SDValue Stride = DAG.getSignedConstant(-ElemWidthByte, DL, XLenVT); MachineFunction &MF = DAG.getMachineFunction(); MachinePointerInfo PtrInfo(VPLoad->getAddressSpace()); @@ -16414,7 +16414,7 @@ static SDValue performVP_STORECombine(SDNode *N, SelectionDAG &DAG, DAG.getConstant(ElemWidthByte, DL, XLenVT)); SDValue Base = DAG.getNode(ISD::ADD, DL, XLenVT, VPStore->getBasePtr(), Temp2); - SDValue Stride = DAG.getConstant(-ElemWidthByte, DL, XLenVT); + SDValue Stride = DAG.getSignedConstant(-ElemWidthByte, DL, XLenVT); MachineFunction &MF = DAG.getMachineFunction(); MachinePointerInfo PtrInfo(VPStore->getAddressSpace()); diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll b/llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll index 50e26bd..24d8e56 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+f,+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+f,+v -verify-machineinstrs < %s | FileCheck %s define <vscale x 2 x float> @test_reverse_load_combiner(<vscale x 2 x float>* %ptr, i32 zeroext %evl) { diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll index 4896a13..a2466c4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+f,+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+f,+v -verify-machineinstrs < %s | FileCheck %s define void @test_store_reverse_combiner(<vscale x 2 x float> %val, <vscale x 2 x float>* %ptr, i32 zeroext %evl) { |