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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-07-04 14:20:58 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-07-04 14:20:58 +0000 |
| commit | 0c3b421b1aaad2c56feb203e52573125e5f218c4 (patch) | |
| tree | 55a26a9bb31c9ccece086d59fd4cfcf2a96efff9 | |
| parent | 089303d8ffeda0426de8c134fc40f0c2bd772abe (diff) | |
| download | llvm-0c3b421b1aaad2c56feb203e52573125e5f218c4.zip llvm-0c3b421b1aaad2c56feb203e52573125e5f218c4.tar.gz llvm-0c3b421b1aaad2c56feb203e52573125e5f218c4.tar.bz2 | |
[X86][SSE] Add v16i16 shl x,c -> pmullw test
llvm-svn: 336277
| -rw-r--r-- | llvm/test/CodeGen/X86/lower-vec-shift.ll | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/X86/lower-vec-shift.ll b/llvm/test/CodeGen/X86/lower-vec-shift.ll index a82bf79..13953b9 100644 --- a/llvm/test/CodeGen/X86/lower-vec-shift.ll +++ b/llvm/test/CodeGen/X86/lower-vec-shift.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+ssse3 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE -; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1 -; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2 +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+ssse3 | FileCheck %s --check-prefixes=CHECK,SSE +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2 ; Verify that the following shifts are lowered into a sequence of two shifts plus ; a blend. On pre-avx2 targets, instead of scalarizing logical and arithmetic @@ -254,3 +254,26 @@ define <8 x i32> @test10(<8 x i32>* %a) { %ashr = ashr <8 x i32> %ld, <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> ret <8 x i32> %ashr } + +define <16 x i16> @test11(<16 x i16> %a) { +; SSE-LABEL: test11: +; SSE: # %bb.0: +; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0 +; SSE-NEXT: pmullw {{.*}}(%rip), %xmm1 +; SSE-NEXT: retq +; +; AVX1-LABEL: test11: +; AVX1: # %bb.0: +; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: test11: +; AVX2: # %bb.0: +; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0 +; AVX2-NEXT: retq + %lshr = shl <16 x i16> %a, <i16 1, i16 3, i16 1, i16 1, i16 1, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 1, i16 1, i16 1, i16 3, i16 1> + ret <16 x i16> %lshr +} |