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| author | Jingu Kang <jingu.kang@arm.com> | 2023-09-05 14:58:59 +0100 |
|---|---|---|
| committer | Jingu Kang <jingu.kang@arm.com> | 2023-09-05 17:57:38 +0100 |
| commit | 06ec1ff2946807b7c3931a86d3541bf00b5441e4 (patch) | |
| tree | b049c0d283b2cb6911482125d2b9168b3345b26a | |
| parent | 282bf213ee2f0fc0c259efa4e9f6283a1f1a2ae1 (diff) | |
| download | llvm-06ec1ff2946807b7c3931a86d3541bf00b5441e4.zip llvm-06ec1ff2946807b7c3931a86d3541bf00b5441e4.tar.gz llvm-06ec1ff2946807b7c3931a86d3541bf00b5441e4.tar.bz2 | |
[AArch64] Replace uaddlv intrinsic with uaddlv sdnode
Differential Revision: https://reviews.llvm.org/D159447
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 2bb8e43..abe1003 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -8740,9 +8740,9 @@ SDValue AArch64TargetLowering::LowerCTPOP_PARITY(SDValue Op, Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val); SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val); - SDValue UaddLV = DAG.getNode( - ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32, - DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, DL, MVT::i32), CtPop); + SDValue UaddLV = DAG.getNode(AArch64ISD::UADDLV, DL, MVT::v4i32, CtPop); + UaddLV = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, UaddLV, + DAG.getConstant(0, DL, MVT::i64)); if (IsParity) UaddLV = DAG.getNode(ISD::AND, DL, MVT::i32, UaddLV, @@ -8755,9 +8755,9 @@ SDValue AArch64TargetLowering::LowerCTPOP_PARITY(SDValue Op, Val = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Val); SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v16i8, Val); - SDValue UaddLV = DAG.getNode( - ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32, - DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, DL, MVT::i32), CtPop); + SDValue UaddLV = DAG.getNode(AArch64ISD::UADDLV, DL, MVT::v4i32, CtPop); + UaddLV = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, UaddLV, + DAG.getConstant(0, DL, MVT::i64)); if (IsParity) UaddLV = DAG.getNode(ISD::AND, DL, MVT::i32, UaddLV, |