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| author | Craig Topper <craig.topper@sifive.com> | 2020-12-15 13:34:04 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2020-12-15 13:54:41 -0800 |
| commit | 028efac2d7c2a32c35a093e53ea12f527edff7c7 (patch) | |
| tree | 0edbb3c82b0e400fab3ca68fadac9a027ade1abc | |
| parent | 95019de8a122619fc038c9fe3c80e625e3456bbf (diff) | |
| download | llvm-028efac2d7c2a32c35a093e53ea12f527edff7c7.zip llvm-028efac2d7c2a32c35a093e53ea12f527edff7c7.tar.gz llvm-028efac2d7c2a32c35a093e53ea12f527edff7c7.tar.bz2 | |
[RISCV] Only custom legalize i32 arguments to vector intrinsics on RV64.
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 529a5bf..c0202e3 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -340,9 +340,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, if (Subtarget.hasStdExtV()) { setBooleanVectorContents(ZeroOrOneBooleanContent); + // RVV intrinsics may have illegal operands. - for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) - setOperationAction(ISD::INTRINSIC_WO_CHAIN, VT, Custom); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i8, Custom); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i16, Custom); + if (Subtarget.is64Bit()) + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom); } // Function alignments. |