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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-03-24 20:27:00 -0400 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-03-24 20:41:01 -0400 |
| commit | 01a337cfc92c57d979939fae9394fbbede63f64b (patch) | |
| tree | a8a489dc7b1d38bc100292623e82b820213c0612 | |
| parent | dca920a904c27f4c86e909ef2e4e343d48168cca (diff) | |
| download | llvm-01a337cfc92c57d979939fae9394fbbede63f64b.zip llvm-01a337cfc92c57d979939fae9394fbbede63f64b.tar.gz llvm-01a337cfc92c57d979939fae9394fbbede63f64b.tar.bz2 | |
AMDGPU/GlobalISel: Add missing tests for G_FRINT selection
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.mir | 105 |
1 files changed, 105 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.mir new file mode 100644 index 0000000..45a8551 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.mir @@ -0,0 +1,105 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=bonaire -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s + +--- +name: frint_s32_vv +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0 + + ; GCN-LABEL: name: frint_s32_vv + ; GCN: liveins: $vgpr0 + ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GCN: [[V_RNDNE_F32_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F32_e64 0, [[COPY]], 0, 0, implicit $exec + ; GCN: $vgpr0 = COPY [[V_RNDNE_F32_e64_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s32) = G_FRINT %0 + $vgpr0 = COPY %1 +... + +--- +name: frint_s32_vs +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $sgpr0 + + ; GCN-LABEL: name: frint_s32_vs + ; GCN: liveins: $sgpr0 + ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GCN: [[V_RNDNE_F32_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F32_e64 0, [[COPY]], 0, 0, implicit $exec + ; GCN: $vgpr0 = COPY [[V_RNDNE_F32_e64_]] + %0:sgpr(s32) = COPY $sgpr0 + %1:vgpr(s32) = G_FRINT %0 + $vgpr0 = COPY %1 +... + +--- +name: frint_fneg_s32_vv +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0 + + ; GCN-LABEL: name: frint_fneg_s32_vv + ; GCN: liveins: $vgpr0 + ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GCN: [[V_RNDNE_F32_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F32_e64 1, [[COPY]], 0, 0, implicit $exec + ; GCN: $vgpr0 = COPY [[V_RNDNE_F32_e64_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s32) = G_FNEG %0 + %2:vgpr(s32) = G_FRINT %1 + $vgpr0 = COPY %2 +... + +--- +name: frint_s64_vv +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0_vgpr1 + + ; GCN-LABEL: name: frint_s64_vv + ; GCN: liveins: $vgpr0_vgpr1 + ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 + ; GCN: [[V_RNDNE_F64_e64_:%[0-9]+]]:vreg_64 = V_RNDNE_F64_e64 0, [[COPY]], 0, 0, implicit $exec + ; GCN: $vgpr0_vgpr1 = COPY [[V_RNDNE_F64_e64_]] + %0:vgpr(s64) = COPY $vgpr0_vgpr1 + %1:vgpr(s64) = G_FRINT %0 + $vgpr0_vgpr1 = COPY %1 +... + +--- +name: frint_s64_fneg_vv +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0_vgpr1 + + ; GCN-LABEL: name: frint_s64_fneg_vv + ; GCN: liveins: $vgpr0_vgpr1 + ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 + ; GCN: [[V_RNDNE_F64_e64_:%[0-9]+]]:vreg_64 = V_RNDNE_F64_e64 1, [[COPY]], 0, 0, implicit $exec + ; GCN: $vgpr0_vgpr1 = COPY [[V_RNDNE_F64_e64_]] + %0:vgpr(s64) = COPY $vgpr0_vgpr1 + %1:vgpr(s64) = G_FNEG %0 + %2:vgpr(s64) = G_FRINT %1 + $vgpr0_vgpr1 = COPY %2 +... |