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| author | Simon Atanasyan <simon@atanasyan.com> | 2019-06-19 22:07:46 +0000 |
|---|---|---|
| committer | Simon Atanasyan <simon@atanasyan.com> | 2019-06-19 22:07:46 +0000 |
| commit | 0121432602233e3b13cd5d9a8632634d78295cbe (patch) | |
| tree | e4553290ad2559647f46d700c618f7c9f47e3104 | |
| parent | 046f855758cd1362c6fa64eb3b877b609fc01c22 (diff) | |
| download | llvm-0121432602233e3b13cd5d9a8632634d78295cbe.zip llvm-0121432602233e3b13cd5d9a8632634d78295cbe.tar.gz llvm-0121432602233e3b13cd5d9a8632634d78295cbe.tar.bz2 | |
[mips] Add (GPR|PTR)_64 predicates to PseudoReturn64 and PseudoIndirectHazardBranch64
This patch is one of a series of patches. The goal is to make P5600
scheduler model complete and turn on the `CompleteModel` flag.
llvm-svn: 363885
| -rw-r--r-- | llvm/lib/Target/Mips/Mips64InstrInfo.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index 51bb2a7..88b71bb 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -274,7 +274,7 @@ let AdditionalPredicates = [NotInMicroMips], def JR_HB64 : JR_HB_DESC<GPR64Opnd>, JR_HB_ENC, ISA_MIPS64_NOT_64R6; def JALR_HB64 : JALR_HB_DESC<GPR64Opnd>, JALR_HB_ENC, ISA_MIPS64R2; } -def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>; +def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>, GPR_64; let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, NoIndirectJumpGuards] in { @@ -290,7 +290,7 @@ let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, ISA_MIPS32R2_NOT_32R6_64R6, PTR_64; def PseudoIndirectHazardBranch64 : PseudoIndirectBranchBase<JR_HB64, GPR64Opnd>, - ISA_MIPS32R2_NOT_32R6_64R6; + ISA_MIPS32R2_NOT_32R6_64R6, PTR_64; } /// Multiply and Divide Instructions. |