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| author | Brandon Wu <brandon.wu@sifive.com> | 2024-03-06 09:12:35 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-03-06 09:12:35 +0800 |
| commit | 2a1b09fee4b4b22f4f7189695ce3e858b91a8d69 (patch) | |
| tree | 372bf20196fd129040795886c65a5189e42ce649 | |
| parent | 6c39e3fa113d2956cb5b5f6769d2ad9a266377e5 (diff) | |
| download | llvm-2a1b09fee4b4b22f4f7189695ce3e858b91a8d69.zip llvm-2a1b09fee4b4b22f4f7189695ce3e858b91a8d69.tar.gz llvm-2a1b09fee4b4b22f4f7189695ce3e858b91a8d69.tar.bz2 | |
[RISCV][SiFive] Add RISCVUsage for SiFive Intelligence Extensions (#84010)
| -rw-r--r-- | llvm/docs/RISCVUsage.rst | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 582b4a5..a1de859 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -332,6 +332,15 @@ The current vendor extensions supported are: ``XSfvcp`` LLVM implements `version 1.0.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification <https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf>`__ by SiFive. All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above. +``XSfvqmaccdod``, ``XSfvqmaccqoq`` + LLVM implements `version 1.1.0 of the SiFive Int8 Matrix Multiplication Extensions Specification <https://sifive.cdn.prismic.io/sifive/1a2ad85b-d818-49f7-ba83-f51f1731edbe_int8-matmul-spec.pdf>`__ by SiFive. All instructions are prefixed with `sf.` as described in the specification linked above. + +``Xsfvfnrclipxfqf`` + LLVM implements `version 1.0.0 of the FP32-to-int8 Ranged Clip Instructions Extension Specification <https://sifive.cdn.prismic.io/sifive/0aacff47-f530-43dc-8446-5caa2260ece0_xsfvfnrclipxfqf-spec.pdf>`__ by SiFive. All instructions are prefixed with `sf.` as described in the specification linked above. + +``Xsfvfwmaccqqq`` + LLVM implements `version 1.0.0 of the Matrix Multiply Accumulate Instruction Extension Specification <https://sifive.cdn.prismic.io/sifive/c391d53e-ffcf-4091-82f6-c37bf3e883ed_xsfvfwmaccqqq-spec.pdf>`__ by SiFive. All instructions are prefixed with `sf.` as described in the specification linked above. + ``XCVbitmanip`` LLVM implements `version 1.0.0 of the CORE-V Bit Manipulation custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst>`__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. |