From 2a1b09fee4b4b22f4f7189695ce3e858b91a8d69 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Wed, 6 Mar 2024 09:12:35 +0800 Subject: [RISCV][SiFive] Add RISCVUsage for SiFive Intelligence Extensions (#84010) --- llvm/docs/RISCVUsage.rst | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 582b4a5..a1de859 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -332,6 +332,15 @@ The current vendor extensions supported are: ``XSfvcp`` LLVM implements `version 1.0.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification `__ by SiFive. All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above. +``XSfvqmaccdod``, ``XSfvqmaccqoq`` + LLVM implements `version 1.1.0 of the SiFive Int8 Matrix Multiplication Extensions Specification `__ by SiFive. All instructions are prefixed with `sf.` as described in the specification linked above. + +``Xsfvfnrclipxfqf`` + LLVM implements `version 1.0.0 of the FP32-to-int8 Ranged Clip Instructions Extension Specification `__ by SiFive. All instructions are prefixed with `sf.` as described in the specification linked above. + +``Xsfvfwmaccqqq`` + LLVM implements `version 1.0.0 of the Matrix Multiply Accumulate Instruction Extension Specification `__ by SiFive. All instructions are prefixed with `sf.` as described in the specification linked above. + ``XCVbitmanip`` LLVM implements `version 1.0.0 of the CORE-V Bit Manipulation custom instructions specification `__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. -- cgit v1.1