aboutsummaryrefslogtreecommitdiff
path: root/sysdeps/x86_64/cacheinfo.c
AgeCommit message (Expand)AuthorFilesLines
2014-08-12Replace cpuid asm statement with __cpuid_countH.J. Lu1-3/+1
2014-01-01Update copyright notices with scripts/update-copyrightsAllan McRae1-1/+1
2013-01-05Change __x86_64 prefix in cache size to __x86H.J. Lu1-27/+27
2013-01-02Update copyright notices with scripts/update-copyrights.Joseph Myers1-1/+1
2012-02-09Replace FSF snail mail address with URLs.Paul Eggert1-4/+2
2011-04-03Fix typo in cache information table for x86-{32,64}.Ulrich Drepper1-1/+1
2011-03-22Last change caused infinite loops because of missing loop increment.Ulrich Drepper1-0/+2
2011-03-20Implement x86 cpuid handling of leaf4 for cache information.Ulrich Drepper1-0/+49
2011-03-04Enable SSE2 memset for AMD'supcoming Orochi processor.Harsha Jagasia1-15/+34
2010-11-0532bit memset-sse2.S fails with uneven cache sizeUlrich Drepper1-2/+18
2010-01-12Optimize 32bit memset/memcpy with SSE2/SSSE3.H.J. Lu1-2/+8
2009-08-07Fix whitespaces in last checkin.Ulrich Drepper1-1/+1
2009-08-07Properly count number of logical processors on Intel CPUs.H.J. Lu1-4/+38
2009-07-31Support multiarch for i686.H.J. Lu1-38/+41
2009-07-23Avoid cpuid instructions in cache info discovery.Ulrich Drepper1-19/+31
2009-07-23Add more cache descriptors for L3 caches on x86 and x86-64.Ulrich Drepper1-0/+3
2009-05-31Simplify CPUID value handling.Ulrich Drepper1-4/+4
2009-05-29Compact cache info data structure for x86/x86-64.Ulrich Drepper1-77/+77
2009-05-10* version.h (VERSION): Bump to 2.10.1.cvs/fedora-glibc-20090510T1842cvs/masterUlrich Drepper1-0/+1
2009-03-13* config.h.in (USE_MULTIARCH): Define.Ulrich Drepper1-4/+28
2009-02-01* sysdeps/x86_64/cacheinfo.c (intel_02_known): Add new descriptors.Ulrich Drepper1-0/+14
2008-03-07* sysdeps/x86_64/rtld-memset.c: New file.Ulrich Drepper1-9/+1
2007-12-23(intel_02_known): New entry 0x3f.Ulrich Drepper1-0/+1
2007-10-17* sysdeps/x86_64/cacheinfo.c: Comment out code added in support ofUlrich Drepper1-0/+8
2007-10-16* sysdeps/x86_64/cacheinfo.c (__x86_64_shared_cache_size): Define.Ulrich Drepper1-4/+26
2007-10-10* sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Work around problemUlrich Drepper1-0/+8
2007-09-22* sysdeps/x86_64/cacheinfo.c (__x86_64_data_cache_size_half): RenamedUlrich Drepper1-18/+58
2007-08-25* sysdeps/x86_64/cacheinfo.c (handle_amd): Fix computation ofcvs/fedora-glibc-20070825T1839Ulrich Drepper1-8/+6
2007-08-25* sysdeps/x86_64/cacheinfo.c (handle_amd): Handle L3 cacheUlrich Drepper1-2/+56
2007-07-09* sysdeps/x86_64/cacheinfo.c (intel_02_known): Add new entries.Ulrich Drepper1-0/+2
2007-05-21* sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Pass correct valueUlrich Drepper1-18/+19
2007-05-21* sysdeps/unix/sysv/linux/x86_64/sysconf.c: Move cache informationUlrich Drepper1-0/+450
generated by cgit v1.1 at 2024-11-22 00:17:43 +0000