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2020-12-30x86 long double: Consider pseudo numbers as signalingSiddhesh Poyarekar1-0/+30
2020-12-24Remove _ISOMAC check from <cpu-features.h>H.J. Lu1-81/+75
2020-12-24x86: Remove the duplicated CPU_FEATURE_CPU_PH.J. Lu1-2/+0
2020-12-24Partially revert 681900d29683722b1cb0a8e565a0585846ec5a61Siddhesh Poyarekar2-12/+1
2020-12-24x86 long double: Support pseudo numbers in isnanlSiddhesh Poyarekar1-0/+45
2020-12-24x86 long double: Support pseudo numbers in fpclassifylSiddhesh Poyarekar1-0/+46
2020-12-22<sys/platform/x86.h>: Add Intel LAM supportH.J. Lu2-0/+4
2020-12-14x86: Remove the default REP MOVSB threshold tunable value [BZ #27061]H.J. Lu1-2/+4
2020-12-11elf: Pass the fd to note processingSzabolcs Nagy1-3/+3
2020-12-04x86: Adjust tst-cpu-features-supports.c for GCC 11H.J. Lu1-5/+10
2020-12-04x86: Set RDRAND usable if CPU supports RDRANDH.J. Lu1-0/+1
2020-11-13x86: Remove UP macro. Define LOCK_PREFIX unconditionally.Florian Weimer1-7/+1
2020-10-28x86: Restore processing of cache size tunables in init_cacheinfoFlorian Weimer1-8/+4
2020-10-28x86: Optimizing memcpy for AMD Zen architecture.Sajan Karumanchi1-6/+26
2020-10-16x86: Initialize CPU info via IFUNC relocation [BZ 26203]H.J. Lu7-857/+943
2020-10-09<sys/platform/x86.h>: Add FSRCS/FSRS/FZLRM supportH.J. Lu3-0/+18
2020-10-09<sys/platform/x86.h>: Add Intel HRESET supportH.J. Lu2-0/+4
2020-10-09<sys/platform/x86.h>: Add AVX-VNNI supportH.J. Lu3-0/+7
2020-10-09<sys/platform/x86.h>: Add AVX512_FP16 supportH.J. Lu3-3/+7
2020-10-09<sys/platform/x86.h>: Add Intel UINTR supportH.J. Lu2-3/+4
2020-09-28Reversing calculation of __x86_shared_non_temporal_thresholdPatrick McGehearty1-5/+11
2020-09-22x86: Harden printf against non-normal long double values (bug 26649)Florian Weimer3-0/+64
2020-09-22x86: Use one ldbl2mpn.c file for both i386 and x86_64Florian Weimer1-0/+120
2020-09-17x86: Use HAS_CPU_FEATURE with IBT and SHSTK [BZ #26625]H.J. Lu3-6/+4
2020-09-16<sys/platform/x86.h>: Add Intel Key Locker supportH.J. Lu3-3/+42
2020-09-11x86: Install <sys/platform/x86.h> [BZ #26124]H.J. Lu8-141/+654
2020-09-03x86: Set CPU usable feature bits conservatively [BZ #26552]H.J. Lu1-96/+47
2020-08-05x86: Rename Intel CPU feature namesH.J. Lu2-15/+15
2020-07-13x86: Support usable check for all CPU featuresH.J. Lu6-439/+561
2020-07-11x86: Remove __ASSEMBLER__ check in init-arch.hH.J. Lu1-5/+1
2020-07-11x86: Remove the unused __x86_prefetchwH.J. Lu2-16/+4
2020-07-08rtld: Clean up PT_NOTE and add PT_GNU_PROPERTY handlingSzabolcs Nagy1-40/+7
2020-07-06x86: Add thresholds for "rep movsb/stosb" to tunablesH.J. Lu4-0/+68
2020-07-06x86: Detect Extended Feature Disable (XFD)H.J. Lu2-0/+4
2020-07-06x86: Correct bit_cpu_CLFSH [BZ #26208]H.J. Lu1-1/+1
2020-06-26x86: Detect Intel Advanced Matrix ExtensionsH.J. Lu3-0/+44
2020-06-22x86: Update CPU feature detection [BZ #26149]H.J. Lu4-389/+267
2020-06-22i386: Use builtin sqrtlAdhemerval Zanella1-0/+27
2020-06-18x86: Update F16C detection [BZ #26133]H.J. Lu2-3/+7
2020-06-17x86: Correct bit_cpu_CLFLUSHOPT [BZ #26128]H.J. Lu1-1/+1
2020-05-21x86: Update Intel Atom processor family optimizationH.J. Lu1-1/+19
2020-05-18x86: Add --enable-cet=permissiveH.J. Lu6-43/+69
2020-05-18x86: Move CET control to _dl_x86_feature_control [BZ #25887]H.J. Lu6-66/+77
2020-05-06semaphore: consolidate arch headers into a generic oneVineet Gupta1-40/+0
2020-04-30i386: Remove unused variable in sysdeps/x86/cacheinfo.cFlorian Weimer1-1/+1
2020-04-30x86: Add the test case of __get_cpu_features support for Zhaoxin processorsmayshao-oc1-0/+2
2020-04-30x86: Add cache information support for Zhaoxin processorsmayshao-oc1-196/+282
2020-04-30x86: Add CPU Vendor ID detection support for Zhaoxin processorsmayshao2-0/+55
2020-04-20Revert "x86_64: Add SSE sfp-exceptions"Adhemerval Zanella1-57/+0
2020-04-17x86_64: Add SSE sfp-exceptionsAdhemerval Zanella1-0/+57
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