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path: root/sysdeps/x86/cpu-features.c
AgeCommit message (Expand)AuthorFilesLines
2022-01-18x86: Black list more Intel CPUs for TSX [BZ #27398]H.J. Lu1-3/+31
2022-01-01Update copyright dates with scripts/update-copyrightsPaul Eggert1-1/+1
2021-12-06x86: Don't set Prefer_No_AVX512 for processors with AVX512 and AVX-VNNIH.J. Lu1-2/+5
2021-11-01x86-64: Remove Prefer_AVX2_STRCMPH.J. Lu1-8/+0
2021-07-28x86-64: Add Avoid_Short_Distance_REP_MOVSBH.J. Lu1-0/+5
2021-07-23x86: Install <bits/platform/x86.h> [BZ #27958]H.J. Lu1-94/+94
2021-07-01x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]H.J. Lu1-1/+4
2021-06-23x86: Copy IBT and SHSTK usable only if CET is enabledH.J. Lu1-2/+5
2021-03-29x86: Set Prefer_No_VZEROUPPER and add Prefer_AVX2_STRCMPH.J. Lu1-2/+18
2021-03-29x86: Properly disable XSAVE related features [BZ #27605]H.J. Lu1-0/+55
2021-02-07x86: Add PTWRITE feature detection [BZ #27346]H.J. Lu1-0/+8
2021-02-01sysconf: Add _SC_MINSIGSTKSZ/_SC_SIGSTKSZ [BZ #20305]H.J. Lu1-0/+3
2021-01-29x86: Properly set usable CET feature bits [BZ #26625]H.J. Lu1-2/+9
2021-01-21<sys/platform/x86.h>: Remove the C preprocessor magicH.J. Lu1-34/+34
2021-01-14x86: Move x86 processor cache info to cpu_featuresH.J. Lu1-27/+8
2021-01-07x86: Support GNU_PROPERTY_X86_ISA_1_V[234] marker [BZ #26717]H.J. Lu1-0/+3
2021-01-02Update copyright dates with scripts/update-copyrightsPaul Eggert1-1/+1
2020-12-04x86: Set RDRAND usable if CPU supports RDRANDH.J. Lu1-0/+1
2020-10-16x86: Initialize CPU info via IFUNC relocation [BZ 26203]H.J. Lu1-1/+11
2020-10-09<sys/platform/x86.h>: Add FSRCS/FSRS/FZLRM supportH.J. Lu1-0/+3
2020-10-09<sys/platform/x86.h>: Add AVX-VNNI supportH.J. Lu1-0/+2
2020-10-09<sys/platform/x86.h>: Add AVX512_FP16 supportH.J. Lu1-0/+2
2020-09-17x86: Use HAS_CPU_FEATURE with IBT and SHSTK [BZ #26625]H.J. Lu1-2/+2
2020-09-16<sys/platform/x86.h>: Add Intel Key Locker supportH.J. Lu1-0/+14
2020-09-03x86: Set CPU usable feature bits conservatively [BZ #26552]H.J. Lu1-96/+47
2020-07-13x86: Support usable check for all CPU featuresH.J. Lu1-187/+249
2020-07-06x86: Add thresholds for "rep movsb/stosb" to tunablesH.J. Lu1-0/+4
2020-06-26x86: Detect Intel Advanced Matrix ExtensionsH.J. Lu1-0/+18
2020-06-22x86: Update CPU feature detection [BZ #26149]H.J. Lu1-68/+88
2020-06-18x86: Update F16C detection [BZ #26133]H.J. Lu1-0/+4
2020-05-21x86: Update Intel Atom processor family optimizationH.J. Lu1-1/+19
2020-05-18x86: Move CET control to _dl_x86_feature_control [BZ #25887]H.J. Lu1-7/+5
2020-04-30x86: Add CPU Vendor ID detection support for Zhaoxin processorsmayshao1-0/+54
2020-01-01Update copyright dates with scripts/update-copyrights.Joseph Myers1-1/+1
2019-09-07Prefer https to http for gnu.org and fsf.org URLsPaul Eggert1-1/+1
2019-02-25Break more lines before not after operators.Joseph Myers1-4/+4
2019-02-12Add fall-through comments.Joseph Myers1-0/+2
2019-01-01Update copyright dates with scripts/update-copyrights.Joseph Myers1-1/+1
2018-12-13x86: Add Hygon Dhyana support.Carlos O'Donell1-2/+3
2018-12-03x86: Extend CPUID support in struct cpu_featuresH.J. Lu1-34/+107
2018-10-23x86: Fix Haswell strong flags (BZ#23709)Adhemerval Zanella1-0/+6
2018-08-02Rename the glibc.tune namespace to glibc.cpuSiddhesh Poyarekar1-3/+3
2018-08-01x86: Rename get_common_indeces to get_common_indicesH.J. Lu1-4/+4
2018-07-26x86: Populate COMMON_CPUID_INDEX_80000001 for Intel CPUs [BZ #23459]H.J. Lu1-9/+18
2018-07-17x86: Always include <dl-cet.h>/cet-tunables.h> for --enable-cetH.J. Lu1-2/+5
2018-07-16x86: Support IBT and SHSTK in Intel CET [BZ #21598]H.J. Lu1-0/+60
2018-07-06Use AVX_Fast_Unaligned_Load from Zen onwards.Amit Pawar1-5/+13
2018-01-01Update copyright dates with scripts/update-copyrights.Joseph Myers1-1/+1
2017-10-20x86-64: Use fxsave/xsave/xsavec in _dl_runtime_resolve [BZ #21265]H.J. Lu1-17/+71
2017-10-19x86-64: Don't set GLRO(dl_platform) to NULL [BZ #22299]H.J. Lu1-4/+8
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