diff options
Diffstat (limited to 'sysdeps')
| -rw-r--r-- | sysdeps/mips/atomic-machine.h | 362 | ||||
| -rw-r--r-- | sysdeps/mips/math-tests.h | 8 |
2 files changed, 43 insertions, 327 deletions
diff --git a/sysdeps/mips/atomic-machine.h b/sysdeps/mips/atomic-machine.h index 16fef6b..3bb39f0 100644 --- a/sysdeps/mips/atomic-machine.h +++ b/sysdeps/mips/atomic-machine.h @@ -55,76 +55,43 @@ typedef uintmax_t uatomic_max_t; # define MIPS_SYNC sync #endif -/* Certain revisions of the R10000 Processor need an LL/SC Workaround - enabled. Revisions before 3.0 misbehave on atomic operations, and - Revs 2.6 and lower deadlock after several seconds due to other errata. - - To quote the R10K Errata: - Workaround: The basic idea is to inhibit the four instructions - from simultaneously becoming active in R10000. Padding all - ll/sc sequences with nops or changing the looping branch in the - routines to a branch likely (which is always predicted taken - by R10000) will work. The nops should go after the loop, and the - number of them should be 28. This number could be decremented for - each additional instruction in the ll/sc loop such as the lock - modifier(s) between the ll and sc, the looping branch and its - delay slot. For typical short routines with one ll/sc loop, any - instructions after the loop could also count as a decrement. The - nop workaround pollutes the cache more but would be a few cycles - faster if all the code is in the cache and the looping branch - is predicted not taken. */ - - -#ifdef _MIPS_ARCH_R10000 -#define R10K_BEQZ_INSN "beqzl" -#else -#define R10K_BEQZ_INSN "beqz" -#endif - #define MIPS_SYNC_STR_2(X) #X #define MIPS_SYNC_STR_1(X) MIPS_SYNC_STR_2(X) #define MIPS_SYNC_STR MIPS_SYNC_STR_1(MIPS_SYNC) -#if __GNUC_PREREQ (4, 8) || defined __mips16 -/* The __atomic_* builtins are available in GCC 4.7 and later, but MIPS - support for their efficient implementation was added only in GCC 4.8. - We still want to use them even with GCC 4.7 for MIPS16 code where we - have no assembly alternative available and want to avoid the __sync_* - builtins if at all possible. */ - -# define USE_ATOMIC_COMPILER_BUILTINS 1 +#define USE_ATOMIC_COMPILER_BUILTINS 1 /* MIPS is an LL/SC machine. However, XLP has a direct atomic exchange instruction which will be used by __atomic_exchange_n. */ -# ifdef _MIPS_ARCH_XLP -# define ATOMIC_EXCHANGE_USES_CAS 0 -# else -# define ATOMIC_EXCHANGE_USES_CAS 1 -# endif +#ifdef _MIPS_ARCH_XLP +# define ATOMIC_EXCHANGE_USES_CAS 0 +#else +# define ATOMIC_EXCHANGE_USES_CAS 1 +#endif /* Compare and exchange. For all "bool" routines, we return FALSE if exchange succesful. */ -# define __arch_compare_and_exchange_bool_8_int(mem, newval, oldval, model) \ +#define __arch_compare_and_exchange_bool_8_int(mem, newval, oldval, model) \ (abort (), 0) -# define __arch_compare_and_exchange_bool_16_int(mem, newval, oldval, model) \ +#define __arch_compare_and_exchange_bool_16_int(mem, newval, oldval, model) \ (abort (), 0) -# define __arch_compare_and_exchange_bool_32_int(mem, newval, oldval, model) \ +#define __arch_compare_and_exchange_bool_32_int(mem, newval, oldval, model) \ ({ \ typeof (*mem) __oldval = (oldval); \ !__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \ model, __ATOMIC_RELAXED); \ }) -# define __arch_compare_and_exchange_val_8_int(mem, newval, oldval, model) \ +#define __arch_compare_and_exchange_val_8_int(mem, newval, oldval, model) \ (abort (), (typeof(*mem)) 0) -# define __arch_compare_and_exchange_val_16_int(mem, newval, oldval, model) \ +#define __arch_compare_and_exchange_val_16_int(mem, newval, oldval, model) \ (abort (), (typeof(*mem)) 0) -# define __arch_compare_and_exchange_val_32_int(mem, newval, oldval, model) \ +#define __arch_compare_and_exchange_val_32_int(mem, newval, oldval, model) \ ({ \ typeof (*mem) __oldval = (oldval); \ __atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \ @@ -132,336 +99,91 @@ typedef uintmax_t uatomic_max_t; __oldval; \ }) -# if _MIPS_SIM == _ABIO32 +#if _MIPS_SIM == _ABIO32 /* We can't do an atomic 64-bit operation in O32. */ -# define __arch_compare_and_exchange_bool_64_int(mem, newval, oldval, model) \ +# define __arch_compare_and_exchange_bool_64_int(mem, newval, oldval, model) \ (abort (), 0) -# define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \ +# define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \ (abort (), (typeof(*mem)) 0) -# else -# define __arch_compare_and_exchange_bool_64_int(mem, newval, oldval, model) \ +#else +# define __arch_compare_and_exchange_bool_64_int(mem, newval, oldval, model) \ __arch_compare_and_exchange_bool_32_int (mem, newval, oldval, model) -# define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \ +# define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \ __arch_compare_and_exchange_val_32_int (mem, newval, oldval, model) -# endif +#endif /* Compare and exchange with "acquire" semantics, ie barrier after. */ -# define atomic_compare_and_exchange_bool_acq(mem, new, old) \ +#define atomic_compare_and_exchange_bool_acq(mem, new, old) \ __atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \ mem, new, old, __ATOMIC_ACQUIRE) -# define atomic_compare_and_exchange_val_acq(mem, new, old) \ +#define atomic_compare_and_exchange_val_acq(mem, new, old) \ __atomic_val_bysize (__arch_compare_and_exchange_val, int, \ mem, new, old, __ATOMIC_ACQUIRE) /* Compare and exchange with "release" semantics, ie barrier before. */ -# define atomic_compare_and_exchange_val_rel(mem, new, old) \ +#define atomic_compare_and_exchange_val_rel(mem, new, old) \ __atomic_val_bysize (__arch_compare_and_exchange_val, int, \ mem, new, old, __ATOMIC_RELEASE) /* Atomic exchange (without compare). */ -# define __arch_exchange_8_int(mem, newval, model) \ +#define __arch_exchange_8_int(mem, newval, model) \ (abort (), (typeof(*mem)) 0) -# define __arch_exchange_16_int(mem, newval, model) \ +#define __arch_exchange_16_int(mem, newval, model) \ (abort (), (typeof(*mem)) 0) -# define __arch_exchange_32_int(mem, newval, model) \ +#define __arch_exchange_32_int(mem, newval, model) \ __atomic_exchange_n (mem, newval, model) -# if _MIPS_SIM == _ABIO32 +#if _MIPS_SIM == _ABIO32 /* We can't do an atomic 64-bit operation in O32. */ -# define __arch_exchange_64_int(mem, newval, model) \ +# define __arch_exchange_64_int(mem, newval, model) \ (abort (), (typeof(*mem)) 0) -# else -# define __arch_exchange_64_int(mem, newval, model) \ +#else +# define __arch_exchange_64_int(mem, newval, model) \ __atomic_exchange_n (mem, newval, model) -# endif +#endif -# define atomic_exchange_acq(mem, value) \ +#define atomic_exchange_acq(mem, value) \ __atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_ACQUIRE) -# define atomic_exchange_rel(mem, value) \ +#define atomic_exchange_rel(mem, value) \ __atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_RELEASE) /* Atomically add value and return the previous (unincremented) value. */ -# define __arch_exchange_and_add_8_int(mem, value, model) \ +#define __arch_exchange_and_add_8_int(mem, value, model) \ (abort (), (typeof(*mem)) 0) -# define __arch_exchange_and_add_16_int(mem, value, model) \ +#define __arch_exchange_and_add_16_int(mem, value, model) \ (abort (), (typeof(*mem)) 0) -# define __arch_exchange_and_add_32_int(mem, value, model) \ +#define __arch_exchange_and_add_32_int(mem, value, model) \ __atomic_fetch_add (mem, value, model) -# if _MIPS_SIM == _ABIO32 +#if _MIPS_SIM == _ABIO32 /* We can't do an atomic 64-bit operation in O32. */ -# define __arch_exchange_and_add_64_int(mem, value, model) \ +# define __arch_exchange_and_add_64_int(mem, value, model) \ (abort (), (typeof(*mem)) 0) -# else -# define __arch_exchange_and_add_64_int(mem, value, model) \ +#else +# define __arch_exchange_and_add_64_int(mem, value, model) \ __atomic_fetch_add (mem, value, model) -# endif +#endif -# define atomic_exchange_and_add_acq(mem, value) \ +#define atomic_exchange_and_add_acq(mem, value) \ __atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \ __ATOMIC_ACQUIRE) -# define atomic_exchange_and_add_rel(mem, value) \ +#define atomic_exchange_and_add_rel(mem, value) \ __atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \ __ATOMIC_RELEASE) -#else /* !__mips16 && !__GNUC_PREREQ (4, 8) */ -/* This implementation using inline assembly will be removed once glibc - requires GCC 4.8 or later to build. */ - -# define USE_ATOMIC_COMPILER_BUILTINS 0 -# define ATOMIC_EXCHANGE_USES_CAS 1 - -/* Compare and exchange. For all of the "xxx" routines, we expect a - "__prev" and a "__cmp" variable to be provided by the enclosing scope, - in which values are returned. */ - -# define __arch_compare_and_exchange_xxx_8_int(mem, newval, oldval, rel, acq) \ - (abort (), __prev = 0, __cmp = 0, (void) __cmp) - -# define __arch_compare_and_exchange_xxx_16_int(mem, newval, oldval, rel, acq) \ - (abort (), __prev = 0, __cmp = 0, (void) __cmp) - -# define __arch_compare_and_exchange_xxx_32_int(mem, newval, oldval, rel, acq) \ - __asm__ __volatile__ ( \ - ".set push\n\t" \ - MIPS_PUSH_MIPS2 \ - rel "\n" \ - "1:\t" \ - "ll %0,%5\n\t" \ - "move %1,$0\n\t" \ - "bne %0,%3,2f\n\t" \ - "move %1,%4\n\t" \ - "sc %1,%2\n\t" \ - R10K_BEQZ_INSN" %1,1b\n" \ - acq "\n\t" \ - ".set pop\n" \ - "2:\n\t" \ - : "=&r" (__prev), "=&r" (__cmp), "=m" (*mem) \ - : "r" (oldval), "r" (newval), "m" (*mem) \ - : "memory") - -# if _MIPS_SIM == _ABIO32 -/* We can't do an atomic 64-bit operation in O32. */ -# define __arch_compare_and_exchange_xxx_64_int(mem, newval, oldval, rel, acq) \ - (abort (), __prev = 0, __cmp = 0, (void) __cmp) -# else -# define __arch_compare_and_exchange_xxx_64_int(mem, newval, oldval, rel, acq) \ - __asm__ __volatile__ ("\n" \ - ".set push\n\t" \ - MIPS_PUSH_MIPS2 \ - rel "\n" \ - "1:\t" \ - "lld %0,%5\n\t" \ - "move %1,$0\n\t" \ - "bne %0,%3,2f\n\t" \ - "move %1,%4\n\t" \ - "scd %1,%2\n\t" \ - R10K_BEQZ_INSN" %1,1b\n" \ - acq "\n\t" \ - ".set pop\n" \ - "2:\n\t" \ - : "=&r" (__prev), "=&r" (__cmp), "=m" (*mem) \ - : "r" (oldval), "r" (newval), "m" (*mem) \ - : "memory") -# endif - -/* For all "bool" routines, we return FALSE if exchange succesful. */ - -# define __arch_compare_and_exchange_bool_8_int(mem, new, old, rel, acq) \ -({ typeof (*mem) __prev __attribute__ ((unused)); int __cmp; \ - __arch_compare_and_exchange_xxx_8_int(mem, new, old, rel, acq); \ - !__cmp; }) - -# define __arch_compare_and_exchange_bool_16_int(mem, new, old, rel, acq) \ -({ typeof (*mem) __prev __attribute__ ((unused)); int __cmp; \ - __arch_compare_and_exchange_xxx_16_int(mem, new, old, rel, acq); \ - !__cmp; }) - -# define __arch_compare_and_exchange_bool_32_int(mem, new, old, rel, acq) \ -({ typeof (*mem) __prev __attribute__ ((unused)); int __cmp; \ - __arch_compare_and_exchange_xxx_32_int(mem, new, old, rel, acq); \ - !__cmp; }) - -# define __arch_compare_and_exchange_bool_64_int(mem, new, old, rel, acq) \ -({ typeof (*mem) __prev __attribute__ ((unused)); int __cmp; \ - __arch_compare_and_exchange_xxx_64_int(mem, new, old, rel, acq); \ - !__cmp; }) - -/* For all "val" routines, return the old value whether exchange - successful or not. */ - -# define __arch_compare_and_exchange_val_8_int(mem, new, old, rel, acq) \ -({ typeof (*mem) __prev; int __cmp; \ - __arch_compare_and_exchange_xxx_8_int(mem, new, old, rel, acq); \ - (typeof (*mem))__prev; }) - -# define __arch_compare_and_exchange_val_16_int(mem, new, old, rel, acq) \ -({ typeof (*mem) __prev; int __cmp; \ - __arch_compare_and_exchange_xxx_16_int(mem, new, old, rel, acq); \ - (typeof (*mem))__prev; }) - -# define __arch_compare_and_exchange_val_32_int(mem, new, old, rel, acq) \ -({ typeof (*mem) __prev; int __cmp; \ - __arch_compare_and_exchange_xxx_32_int(mem, new, old, rel, acq); \ - (typeof (*mem))__prev; }) - -# define __arch_compare_and_exchange_val_64_int(mem, new, old, rel, acq) \ -({ typeof (*mem) __prev; int __cmp; \ - __arch_compare_and_exchange_xxx_64_int(mem, new, old, rel, acq); \ - (typeof (*mem))__prev; }) - -/* Compare and exchange with "acquire" semantics, ie barrier after. */ - -# define atomic_compare_and_exchange_bool_acq(mem, new, old) \ - __atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \ - mem, new, old, "", MIPS_SYNC_STR) - -# define atomic_compare_and_exchange_val_acq(mem, new, old) \ - __atomic_val_bysize (__arch_compare_and_exchange_val, int, \ - mem, new, old, "", MIPS_SYNC_STR) - -/* Compare and exchange with "release" semantics, ie barrier before. */ - -# define atomic_compare_and_exchange_val_rel(mem, new, old) \ - __atomic_val_bysize (__arch_compare_and_exchange_val, int, \ - mem, new, old, MIPS_SYNC_STR, "") - - - -/* Atomic exchange (without compare). */ - -# define __arch_exchange_xxx_8_int(mem, newval, rel, acq) \ - (abort (), (typeof(*mem)) 0) - -# define __arch_exchange_xxx_16_int(mem, newval, rel, acq) \ - (abort (), (typeof(*mem)) 0) - -# define __arch_exchange_xxx_32_int(mem, newval, rel, acq) \ -({ typeof (*mem) __prev; int __cmp; \ - __asm__ __volatile__ ("\n" \ - ".set push\n\t" \ - MIPS_PUSH_MIPS2 \ - rel "\n" \ - "1:\t" \ - "ll %0,%4\n\t" \ - "move %1,%3\n\t" \ - "sc %1,%2\n\t" \ - R10K_BEQZ_INSN" %1,1b\n" \ - acq "\n\t" \ - ".set pop\n" \ - "2:\n\t" \ - : "=&r" (__prev), "=&r" (__cmp), "=m" (*mem) \ - : "r" (newval), "m" (*mem) \ - : "memory"); \ - __prev; }) - -# if _MIPS_SIM == _ABIO32 -/* We can't do an atomic 64-bit operation in O32. */ -# define __arch_exchange_xxx_64_int(mem, newval, rel, acq) \ - (abort (), (typeof(*mem)) 0) -# else -# define __arch_exchange_xxx_64_int(mem, newval, rel, acq) \ -({ typeof (*mem) __prev; int __cmp; \ - __asm__ __volatile__ ("\n" \ - ".set push\n\t" \ - MIPS_PUSH_MIPS2 \ - rel "\n" \ - "1:\n" \ - "lld %0,%4\n\t" \ - "move %1,%3\n\t" \ - "scd %1,%2\n\t" \ - R10K_BEQZ_INSN" %1,1b\n" \ - acq "\n\t" \ - ".set pop\n" \ - "2:\n\t" \ - : "=&r" (__prev), "=&r" (__cmp), "=m" (*mem) \ - : "r" (newval), "m" (*mem) \ - : "memory"); \ - __prev; }) -# endif - -# define atomic_exchange_acq(mem, value) \ - __atomic_val_bysize (__arch_exchange_xxx, int, mem, value, "", MIPS_SYNC_STR) - -# define atomic_exchange_rel(mem, value) \ - __atomic_val_bysize (__arch_exchange_xxx, int, mem, value, MIPS_SYNC_STR, "") - - -/* Atomically add value and return the previous (unincremented) value. */ - -# define __arch_exchange_and_add_8_int(mem, newval, rel, acq) \ - (abort (), (typeof(*mem)) 0) - -# define __arch_exchange_and_add_16_int(mem, newval, rel, acq) \ - (abort (), (typeof(*mem)) 0) - -# define __arch_exchange_and_add_32_int(mem, value, rel, acq) \ -({ typeof (*mem) __prev; int __cmp; \ - __asm__ __volatile__ ("\n" \ - ".set push\n\t" \ - MIPS_PUSH_MIPS2 \ - rel "\n" \ - "1:\t" \ - "ll %0,%4\n\t" \ - "addu %1,%0,%3\n\t" \ - "sc %1,%2\n\t" \ - R10K_BEQZ_INSN" %1,1b\n" \ - acq "\n\t" \ - ".set pop\n" \ - "2:\n\t" \ - : "=&r" (__prev), "=&r" (__cmp), "=m" (*mem) \ - : "r" (value), "m" (*mem) \ - : "memory"); \ - __prev; }) - -# if _MIPS_SIM == _ABIO32 -/* We can't do an atomic 64-bit operation in O32. */ -# define __arch_exchange_and_add_64_int(mem, value, rel, acq) \ - (abort (), (typeof(*mem)) 0) -# else -# define __arch_exchange_and_add_64_int(mem, value, rel, acq) \ -({ typeof (*mem) __prev; int __cmp; \ - __asm__ __volatile__ ( \ - ".set push\n\t" \ - MIPS_PUSH_MIPS2 \ - rel "\n" \ - "1:\t" \ - "lld %0,%4\n\t" \ - "daddu %1,%0,%3\n\t" \ - "scd %1,%2\n\t" \ - R10K_BEQZ_INSN" %1,1b\n" \ - acq "\n\t" \ - ".set pop\n" \ - "2:\n\t" \ - : "=&r" (__prev), "=&r" (__cmp), "=m" (*mem) \ - : "r" (value), "m" (*mem) \ - : "memory"); \ - __prev; }) -# endif - -# define atomic_exchange_and_add_acq(mem, value) \ - __atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \ - "", MIPS_SYNC_STR) - -# define atomic_exchange_and_add_rel(mem, value) \ - __atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \ - MIPS_SYNC_STR, "") - -#endif /* !__mips16 && !__GNUC_PREREQ (4, 8) */ - /* TODO: More atomic operations could be implemented efficiently; only the basic requirements are done. */ diff --git a/sysdeps/mips/math-tests.h b/sysdeps/mips/math-tests.h index 7680db2..8a1055f 100644 --- a/sysdeps/mips/math-tests.h +++ b/sysdeps/mips/math-tests.h @@ -19,10 +19,7 @@ #include <features.h> #include <sgidefs.h> -/* MIPS soft float does not support exceptions and rounding modes, and - before GCC 4.9 long double when wider than double is implemented - using fp-bit which does not integrate with hardware exceptions and - rounding modes. */ +/* MIPS soft float does not support exceptions and rounding modes. */ #ifdef __mips_soft_float # define ROUNDING_TESTS_float(MODE) ((MODE) == FE_TONEAREST) # define ROUNDING_TESTS_double(MODE) ((MODE) == FE_TONEAREST) @@ -30,9 +27,6 @@ # define EXCEPTION_TESTS_float 0 # define EXCEPTION_TESTS_double 0 # define EXCEPTION_TESTS_long_double 0 -#elif _MIPS_SIM != _ABIO32 && !__GNUC_PREREQ (4, 9) -# define ROUNDING_TESTS_long_double(MODE) ((MODE) == FE_TONEAREST) -# define EXCEPTION_TESTS_long_double 0 #endif /* NaN payload preservation when converting a signaling NaN to quiet |