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authorTejas Belagod <Tejas.Belagod@arm.com>2022-06-27 18:00:50 +0000
committerSzabolcs Nagy <szabolcs.nagy@arm.com>2022-06-30 14:01:08 +0100
commite9dd3682963a7038d699430e3ece68045b6caafc (patch)
tree6291bcded33b627d881c13aa161cd4329b12b4b6 /sysdeps
parent71d87d85bf54f6522813aec97c19bdd24997341e (diff)
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AArch64: Add asymmetric faulting mode for tag violations in mem.tagging tunable
The new asymmetric mode is available when HWCAP2_MTE3 is set (support is available), bit2 is set in the tunable (user request per application), and the system is configured such that the asymmetric mode is preferred over sync or async (per-cpu system-wide setting). Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
Diffstat (limited to 'sysdeps')
-rw-r--r--sysdeps/unix/sysv/linux/aarch64/cpu-features.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index 41dda8d..d14c0f4 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -108,7 +108,13 @@ init_cpu_features (struct cpu_features *cpu_features)
TUNABLE_SET (glibc, mem, tagging, cpu_features->mte_state);
# endif
- if (cpu_features->mte_state & 2)
+ if (cpu_features->mte_state & 4)
+ /* Enable choosing system-preferred faulting mode. */
+ __prctl (PR_SET_TAGGED_ADDR_CTRL,
+ (PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC
+ | MTE_ALLOWED_TAGS),
+ 0, 0, 0);
+ else if (cpu_features->mte_state & 2)
__prctl (PR_SET_TAGGED_ADDR_CTRL,
(PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | MTE_ALLOWED_TAGS),
0, 0, 0);