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authorFlorian Weimer <fweimer@redhat.com>2020-11-13 15:19:41 +0100
committerFlorian Weimer <fweimer@redhat.com>2020-11-13 15:20:07 +0100
commitd5c4cce9c3eb82cb57d01a3ce3a0999e146abd63 (patch)
tree366d6fc8a1e10ec1cd553d8a70a67f5f740fa052 /sysdeps/powerpc
parent0f34d426acf8950599ab8a1e6a733fe4c40903a4 (diff)
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powerpc: Eliminate UP macro conditionals
The macro is never defined. Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Diffstat (limited to 'sysdeps/powerpc')
-rw-r--r--sysdeps/powerpc/atomic-machine.h11
-rw-r--r--sysdeps/powerpc/powerpc32/atomic-machine.h4
-rw-r--r--sysdeps/powerpc/powerpc64/atomic-machine.h4
3 files changed, 5 insertions, 14 deletions
diff --git a/sysdeps/powerpc/atomic-machine.h b/sysdeps/powerpc/atomic-machine.h
index bd357a4..4feb215 100644
--- a/sysdeps/powerpc/atomic-machine.h
+++ b/sysdeps/powerpc/atomic-machine.h
@@ -53,14 +53,9 @@ typedef uintmax_t uatomic_max_t;
#define __arch_compare_and_exchange_bool_16_acq(mem, newval, oldval) \
(abort (), 0)
-#ifdef UP
-# define __ARCH_ACQ_INSTR ""
-# define __ARCH_REL_INSTR ""
-#else
-# define __ARCH_ACQ_INSTR "isync"
-# ifndef __ARCH_REL_INSTR
-# define __ARCH_REL_INSTR "sync"
-# endif
+#define __ARCH_ACQ_INSTR "isync"
+#ifndef __ARCH_REL_INSTR
+# define __ARCH_REL_INSTR "sync"
#endif
#ifndef MUTEX_HINT_ACQ
diff --git a/sysdeps/powerpc/powerpc32/atomic-machine.h b/sysdeps/powerpc/powerpc32/atomic-machine.h
index 61c7949..066759d 100644
--- a/sysdeps/powerpc/powerpc32/atomic-machine.h
+++ b/sysdeps/powerpc/powerpc32/atomic-machine.h
@@ -105,9 +105,7 @@
/*
* "light weight" sync can also be used for the release barrier.
*/
-# ifndef UP
-# define __ARCH_REL_INSTR "lwsync"
-# endif
+# define __ARCH_REL_INSTR "lwsync"
# define atomic_write_barrier() __asm ("lwsync" ::: "memory")
#else
/*
diff --git a/sysdeps/powerpc/powerpc64/atomic-machine.h b/sysdeps/powerpc/powerpc64/atomic-machine.h
index 421dbd1..c9372a8 100644
--- a/sysdeps/powerpc/powerpc64/atomic-machine.h
+++ b/sysdeps/powerpc/powerpc64/atomic-machine.h
@@ -230,9 +230,7 @@
/*
* "light weight" sync can also be used for the release barrier.
*/
-#ifndef UP
-# define __ARCH_REL_INSTR "lwsync"
-#endif
+#define __ARCH_REL_INSTR "lwsync"
#define atomic_write_barrier() __asm ("lwsync" ::: "memory")
/*