Update.

1998-05-30  Philip Blundell  <Philip.Blundell@pobox.com>

	* stdlib/gmp-impl.h: Support strange mixed-endian double format
	used by ARM systems.
	* sysdeps/arm/fpu/bits/fenv.h (FE_EXCEPTION_SHIFT): Rename to
	FE_EXCEPT_SHIFT.
	* sysdeps/arm/bits/fenv.h: Deleted.
	* sysdeps/arm/fpu/ieee754.h: New file.
	* sysdeps/arm/gmp-mparam.h: New file.
	* stdlib/longlong.h (umul_ppmm): Temporarily disable broken ARM
	implementation.

4 files changed, 146 insertions, 91 deletions

diff --git a/sysdeps/arm/bits/fenv.h b/sysdeps/arm/bits/fenv.h
deleted file mode 100644
index 3e4cdd3..0000000
--- a/sysdeps/arm/bits/fenv.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Copyright (C) 1997, 1998 Free Software Foundation, Inc.
-   This file is part of the GNU C Library.
-
-   The GNU C Library is free software; you can redistribute it and/or
-   modify it under the terms of the GNU Library General Public License as
-   published by the Free Software Foundation; either version 2 of the
-   License, or (at your option) any later version.
-
-   The GNU C Library is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-   Library General Public License for more details.
-
-   You should have received a copy of the GNU Library General Public
-   License along with the GNU C Library; see the file COPYING.LIB.  If not,
-   write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
-
-#ifndef _FENV_H
-# error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
-#endif
-
-
-/* Define bits representing the exception.  We use the bit positions
-   of the appropriate bits in the FPU control word.  */
-enum
-  {
-    FE_INVALID = 0x01,
-#define FE_INVALID	FE_INVALID
-    __FE_DENORM = 0x02,
-    FE_DIVBYZERO = 0x04,
-#define FE_DIVBYZERO	FE_DIVBYZERO
-    FE_OVERFLOW = 0x08,
-#define FE_OVERFLOW	FE_OVERFLOW
-    FE_UNDERFLOW = 0x10,
-#define FE_UNDERFLOW	FE_UNDERFLOW
-    FE_INEXACT = 0x20
-#define FE_INEXACT	FE_INEXACT
-  };
-
-#define FE_ALL_EXCEPT \
-	(FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)
-
-/* The ARM FPU supports all of the four defined rounding modes.  We
-   use again the bit positions in the FPU control word as the values
-   for the appropriate macros.  */
-enum
-  {
-    FE_TONEAREST = 0,
-#define FE_TONEAREST	FE_TONEAREST
-    FE_DOWNWARD = 0x400,
-#define FE_DOWNWARD	FE_DOWNWARD
-    FE_UPWARD = 0x800,
-#define FE_UPWARD	FE_UPWARD
-    FE_TOWARDSZERO = 0xc00
-#define FE_TOWARDSZERO	FE_TOWARDSZERO
-  };
-
-
-/* Type representing exception flags.  */
-typedef unsigned short int fexcept_t;
-
-
-/* Type representing floating-point environment.  This function corresponds
-   to the layout of the block written by the `fstenv'.  */
-typedef struct
-  {
-    unsigned short int control_word;
-    unsigned short int __unused1;
-    unsigned short int status_word;
-    unsigned short int __unused2;
-    unsigned short int tags;
-    unsigned short int __unused3;
-    unsigned int eip;
-    unsigned short int cs_selector;
-    unsigned int opcode:11;
-    unsigned int __unused4:5;
-    unsigned int data_offset;
-    unsigned short int data_selector;
-    unsigned short int __unused5;
-  }
-fenv_t;
-
-/* If the default argument is used we use this value.  */
-#define FE_DFL_ENV	((fenv_t *) -1)
-
-#ifdef __USE_GNU
-/* Floating-point environment where none of the exception is masked.  */
-# define FE_NOMASK_ENV	((fenv_t *) -2)
-#endif
diff --git a/sysdeps/arm/fpu/bits/fenv.h b/sysdeps/arm/fpu/bits/fenv.h
index 17b9702..ca06196 100644
--- a/sysdeps/arm/fpu/bits/fenv.h
+++ b/sysdeps/arm/fpu/bits/fenv.h
@@ -34,7 +34,7 @@ enum
   };
 
 /* Amount to shift by to convert an exception to a mask bit.  */
-#define FE_EXCEPTION_SHIFT		16
+#define FE_EXCEPT_SHIFT		16
 
 /* All supported exceptions.  */
 #define FE_ALL_EXCEPT	\
diff --git a/sysdeps/arm/fpu/ieee754.h b/sysdeps/arm/fpu/ieee754.h
new file mode 100644
index 0000000..73f7d6a
--- /dev/null
+++ b/sysdeps/arm/fpu/ieee754.h
@@ -0,0 +1,115 @@
+/* Copyright (C) 1992, 1995, 1996, 1998 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Library General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Library General Public License for more details.
+
+   You should have received a copy of the GNU Library General Public
+   License along with the GNU C Library; see the file COPYING.LIB.  If not,
+   write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+#ifndef _IEEE754_H
+
+#define _IEEE754_H 1
+#include <features.h>
+
+#include <endian.h>
+
+__BEGIN_DECLS
+
+union ieee754_float
+  {
+    float f;
+
+    /* This is the IEEE 754 single-precision format.  */
+    struct
+      {
+	unsigned int mantissa:23;
+	unsigned int exponent:8;
+	unsigned int negative:1;
+      } ieee;
+
+    /* This format makes it easier to see if a NaN is a signalling NaN.  */
+    struct
+      {
+	unsigned int mantissa:22;
+	unsigned int quiet_nan:1;
+	unsigned int exponent:8;
+	unsigned int negative:1;
+      } ieee_nan;
+  };
+
+#define IEEE754_FLOAT_BIAS	0x7f /* Added to exponent.  */
+
+
+union ieee754_double
+  {
+    double d;
+
+    /* This is the IEEE 754 double-precision format.  */
+    struct
+      {
+	unsigned int mantissa0:20;
+	unsigned int exponent:11;
+	unsigned int negative:1;
+	unsigned int mantissa1:32;
+      } ieee;
+
+    /* This format makes it easier to see if a NaN is a signalling NaN.  */
+    struct
+      {
+	unsigned int mantissa0:19;
+	unsigned int quiet_nan:1;
+	unsigned int exponent:11;
+	unsigned int negative:1;
+	unsigned int mantissa1:32;
+      } ieee_nan;
+  };
+
+#define IEEE754_DOUBLE_BIAS	0x3ff /* Added to exponent.  */
+
+
+/* The following two structures are correct for `new' floating point systems but
+   wrong for the old FPPC.  The only solution seems to be to avoid their use on
+   old hardware.  */
+
+union ieee854_long_double
+  {
+    long double d;
+
+    /* This is the IEEE 854 double-extended-precision format.  */
+    struct
+      {
+	unsigned int exponent:15;
+	unsigned int empty:16;
+	unsigned int negative:1;
+	unsigned int mantissa1:32;
+	unsigned int mantissa0:32;
+      } ieee;
+
+    /* This is for NaNs in the IEEE 854 double-extended-precision format.  */
+    struct
+      {
+	unsigned int exponent:15;
+	unsigned int empty:16;
+	unsigned int negative:1;
+	unsigned int mantissa1:32;
+	unsigned int mantissa0:30;
+	unsigned int quiet_nan:1;
+	unsigned int one:1;
+      } ieee_nan;
+  };
+
+#define IEEE854_LONG_DOUBLE_BIAS 0x3fff
+
+__END_DECLS
+
+#endif /* ieee754.h */
diff --git a/sysdeps/arm/gmp-mparam.h b/sysdeps/arm/gmp-mparam.h
new file mode 100644
index 0000000..e57f39c
--- /dev/null
+++ b/sysdeps/arm/gmp-mparam.h
@@ -0,0 +1,30 @@
+/* gmp-mparam.h -- Compiler/machine parameter header file.
+
+Copyright (C) 1991, 1993, 1994, 1995 Free Software Foundation, Inc.
+
+This file is part of the GNU MP Library.
+
+The GNU MP Library is free software; you can redistribute it and/or modify
+it under the terms of the GNU Library General Public License as published by
+the Free Software Foundation; either version 2 of the License, or (at your
+option) any later version.
+
+The GNU MP Library is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Library General Public
+License for more details.
+
+You should have received a copy of the GNU Library General Public License
+along with the GNU MP Library; see the file COPYING.LIB.  If not, write to
+the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston,
+MA 02111-1307, USA. */
+
+#define BITS_PER_MP_LIMB 32
+#define BYTES_PER_MP_LIMB 4
+#define BITS_PER_LONGINT 32
+#define BITS_PER_INT 32
+#define BITS_PER_SHORTINT 16
+#define BITS_PER_CHAR 8
+
+#define IEEE_DOUBLE_BIG_ENDIAN 0
+#define IEEE_DOUBLE_MIXED_ENDIAN 1